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Our SoC device supports both external NAND devices as well as Multi-IO/QSPI NOR devices. I can use either of them. Now, for NAND device, it will store only Program Code and Const Data. That means SoC will never write anything back to NAND device. It will always read from the NAND device. Do I need to implemented Wear Leveling as well as Bad Block Management support within the SoC software as NAND device is purely being used as Read-Only Mode device always? Will there be Bit-Flipping Error possible in the NAND device in this mode of operation? Thank you. Regards Pashan

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Reading the device causes no damage of any type. Writing the device is a different matter and there's a description and a band diagram that describes the electrical conditions required for injection that puts traps in the oxide.

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  • \$\begingroup\$ So, as long as NAND Flash is used within the system in Read Only mode, it's reliability related behavior is comparable to NOR Flash devices. Is that always true under temperature/voltage/process variation within the specification limit? Thank you. Regards Pashan \$\endgroup\$ – user3806728 Aug 21 '17 at 21:07
  • \$\begingroup\$ @user3806728 This will be always true. PVT are not really issues that you need worry yourself about if you have a discrete IC. Most of my circuits are designed to be robust to PVT, and that is a circuit designer problem and not a user problem. \$\endgroup\$ – b degnan Aug 22 '17 at 11:14

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