Is it true that 50ohm characteristic impedance is a convention followed for signal carrying PCB tracks? Also, are the IC I/O buffers also designed to have a close to 50ohm impedance to match this?
Very few do. If your chip's datasheet does not say it has 50-ohm termination, then it almost certainly does not.
Traditional CMOS and TTL logic does not provide matching termination, though a few specialized types (line drivers?) might. Typically drivers are low impedance and receivers are high impedance (with some capacitance).
Traditional ECL (emitter-coupled logic) logic does not provide matching termination, though this family is often used at frequencies where (external) termination is desirable. Typically drivers are about 5 ohms, and receivers 2 or 3 kohms. Some newer parts designed for very high frequencies (above 2 Gb/s?) may provide on-chip termination for inputs (which may require an external connection to set a termination voltage).
CML is the one logic type that I know of that typically does provide matched sources and receivers.
LVDS I don't use enough to know what's typical.
For RF chips, consult the datasheet. Some will and others won't provide on-chip termination.
One advantage of not having on-chip termination is that this leaves the user free to use an alternative trace impedance like 75 or 85 ohms. It also allows multiple receivers to be connected to a single driver.
No, the 50-Ohms is not a convention for PCB tracks to carry signals. The 50 Ohms is a standard for coaxial cables and corresponding interconnects - dozens and dozens various SMA/SMB, BNC, type-N, etc. connectors.
In fact, typical (thin) PCB traces have 65 - 80 - 100 Ohm characteristic impedance on a typical stack-up (7 mils or 12 mils of FR4 between ground plane and signal layer). Thin traces are usually needed to maintain reasonable component density on a PCB.
However, if a high-quality high-frequency I/O is required to match the 50 Ohms interconnect, a special care needs to be taken, thin substarates and wider traces must be designed, which takes much more board space, and therefore adds cost.
The matching of impedance usually needed at frequencies of 100MHz and above, which is not the case for many MCU applications. Therefore there no need to waste money on what is not needed.
Simple digital logic (CMOS, TTL) uses simple output buffers, just a complementary pair of properly sized FETs, to provide certain drive current. In a low-power CMOS ICs the typical drive strength is 2 mA - 4 mA. This will give a reasonable match to drive 80-100 Ohm traces nicely. A driver with 6 - 8 mA of drive strength provides reasonable approximation to a 50-Ohm driver. Driver stages that deliver 25 mA or more need a matching network to work with 50-Ohm nets. And still the waveforms will be far from perfect, because the impedance of output transistors is not a constant during signal switch.
A true impedance-controlled (and slew rate controlled) output buffer consists of HUNDREDS of transistors, if not more. About a dozen (or two) of them are used as multi-stage ladders, while the rest provides various timings to gradual (sequential) control for the output stages, and an interface logic (registers and means to access them securely) to store user-defined controls. These buffers usually have a common (for a bus or a lane) calibration circuit (using one or a pair of external resistors), which sets some analog circuitry and provides required value for termination. Many designs include complicated circuitry implementing automatic re-calibration of drivers in case of voltage/temperature changes. All this is not cheap and takes silicon real estate, and is the reason why not every MCU has its I/O impedance-controlled.
It's a convention, but we have lots of conventions.
You mentioned DDR3, so here's Altera on the subject.
The DDR3 SDRAM uses a programmable impedance output buffer. Currently, there are two drive strength settings, 34Ω and 40Ω.
.. but their later diagrams show 50Ω traces and on-die termination ("ODT").
USB requires 90Ω differential impedance.
Suppose you have 2.5 volt swings at 50_ohm impedance. Suppose you have 16 of those traces. 1volt and 50 ohm requires 20mA; 2.5v requires 50mA. 16 of those signals require 800 milliAmps.
Swinging that much current in 1 nanosecond, across 1nanoHenry total inductance (if you can achieve that low), still generates 0.8 volt upset in the onchip rail, whether GND or VDD (MCU driving low or MCU driving high).
Thus several dedicated VDD/GND pairs are dedicated to such wide data busses. Costly in pin usage.
However, suppose the traces are 50pF each, needing to swing 2.5 volts in 1nanosecond. What is the current?
$$I = C * dV/dT$$
or I = 50pF * 2.5v/1nS = 125 milliamp per each of the 16 outputs.
Thus 50 Ohms may not be the problem. The trace/ESD capacitances become the challenge.