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I have a situation where reference clock of PLL_0 is coming from some clock source and giving out a clock (named C0) with freq0 and and C0 is going as reference clock to PLL_1 and giving out clock C1 and C1 is going to PLL_2 and giving out C2.

Please see the below figure for better understanding.

schematic

simulate this circuit – Schematic created using CircuitLab

In the above situation can we say that clocks C2, C1 and C0 are synchronous to each other?

Note: I would like to add that freq0, freq1 and freq2 are not integer multiple of each other.

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    \$\begingroup\$ Clocks are asynchronous when not in-phase or their frequencies are not multiple of the other. \$\endgroup\$ – lucas92 Aug 23 '17 at 13:56
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    \$\begingroup\$ Why do you need this word? They are certainly not independent but it would look to be a lot of hassle to interface other things using single cycles of the various clocks. \$\endgroup\$ – user117772 Aug 23 '17 at 17:22
  • \$\begingroup\$ The only way C0, C1, and C2 would be synchronous (to a "high" degree), would be if Clock Source is the input to all three (they would be in parallel, not series), and the frequencies are integer multiples of the Source frequency. \$\endgroup\$ – Guill Aug 25 '17 at 3:33
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To my understanding meaning of "asynchronous"/"synchronous" may vary depending on the context but in very most cases synchronous means that events happen at a fixed phase relation.

So in your case I'd say yes, the clocks are synchronous because phases are fixed (=locked < Phase Locked Loops), although they may have different frequencies and although there may be some small jitter (phase noise).

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  • \$\begingroup\$ If frequencies are not integer multiple of each other, does the phase locking still come into consideration? \$\endgroup\$ – ssgr Aug 23 '17 at 14:07
  • \$\begingroup\$ As Long as the ratio is a rational number I'd say yes. \$\endgroup\$ – Curd Aug 23 '17 at 14:08
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    \$\begingroup\$ If \$f_0 / f_1 = T_1 / T_0 = m / n\$ (where \$m\$ and \$n\$ are more or less small integers) look at phases of events with respect to frequency \$f = \frac{1}{T_0 T_1}\$. After \$T=T_0 T_1\$ all periodic events will happen again (repeat) with same phases. \$\endgroup\$ – Curd Aug 23 '17 at 14:15
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    \$\begingroup\$ @pipe: and I'd be curious about the implementation of a PLL that is able to generate irrational frequency ratios. \$\endgroup\$ – Curd Aug 23 '17 at 14:20
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    \$\begingroup\$ Yup, I agree, but synchronous is one of those black and white things... it either is or it isn't. With a PLL it really hardly ever is, rather it oscillates around synchronism. BUt it depends on what you do with the clocks too, in many instances it's close enough. \$\endgroup\$ – Trevor_G Aug 23 '17 at 16:47
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can we say that clocks C2, C1 and C0 are synchronous

Yes. The whole point of a PLL is to "lock" one frequency to another (phase, actually, but it turns out to fix the frequency too). They could be asynchronous if the PLLs are malfunctioning, in which case the output from the PLL could be a free-running clock (worst case).

Two clocks are asynchronous if they do not depend on each other, for example two free-standing oscillators at the exact same frequency will still be asynchronous, since you will always have a small amount of drift and an unknown phase at startup.

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I would be very cautious in stating that the frequencies are synchronous.

With ideal PLLs that had no phase jitter then you may be able to make that claim, but in reality there will be some variation in the clock edge timing. As such, if you were driving logic using multiple clocks there may be asynchronous race conditions dictated by that phase jitter.

The clocks may be "in-tune" but synchronous is an over-statement. In reality, a PLL will be in a continual state of going in and out of synchronism. Whether that is "close enough" with a specific design of PLL for your particular requirements is another matter.

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  • \$\begingroup\$ So what's YOUR defintion of synchronous then? \$\endgroup\$ – Curd Aug 23 '17 at 16:40
  • \$\begingroup\$ @Curd same as yours, it's just that real PLLs don't quite give you that "fixed phase relation". They do over n-cycles, but not cycle to cycle. \$\endgroup\$ – Trevor_G Aug 23 '17 at 16:53
  • \$\begingroup\$ A very good and not only hypothetical distinction. \$\endgroup\$ – pipe Aug 23 '17 at 17:00
  • \$\begingroup\$ @Trevor: but also clocks derived from other clocks not by PLL but by counters (or any other combination of logic gates) do have some added jitter (as you can never guarantee that gates will switch at exactly the same threshold). The jitter is just much smaller than that of PLLs. It's just difference in quantity not quality. \$\endgroup\$ – Curd Aug 23 '17 at 17:07
  • \$\begingroup\$ @Curd true, but divider type circuits tend to have fixed rise and fall phase delays so have that "fixed phase relation". Anyhoos.. you get my point, "some caution is pertinent". \$\endgroup\$ – Trevor_G Aug 23 '17 at 17:10
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Just judging from a dictionary definition, I would say these are only synchronous for a likely tiny fraction of the time. Synchronous means happening at the same time. These PLL's tick to the same beat once in a blue moon if they're not integer multiples of each other. For 99.99%+ of the time they are asynchronous. There's no logic you could drive from these separate blocks that you could ever call synchronous. Within each of the PLL's domains, you can have synchronous logic, but if you're looking at all of your logic combined with all 3 of the PLL's domains, it becomes asynchronous to each other.

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    \$\begingroup\$ I agree. Especially if independent clock trees are created for each PLL you have to consider them asynchronous to each other. \$\endgroup\$ – Michael Aug 23 '17 at 19:39
  • \$\begingroup\$ Two clocks being synchronous does NOT mean that both clock signals must have edges at the same time. \$\endgroup\$ – Curd Aug 23 '17 at 22:13
  • \$\begingroup\$ @Curd That's the only way synchronous logic will work together. \$\endgroup\$ – horta Aug 23 '17 at 22:14
  • \$\begingroup\$ According to your understanding a 2MHz clock and a 1MHz clock derived from the first by a divide-by-2 clock divider can not be synchronous because clock edges do not happen at same times. \$\endgroup\$ – Curd Aug 23 '17 at 22:24
  • \$\begingroup\$ @Curd Indeed. They are now asynchronous. That's the only way digital logic will work together which is the main area where I've heard synchronous vs asynchronous. 1MHz logic doesn't interact with 2MHz logic unless you've got special asynchronous mechanisms in place to account for this difference. \$\endgroup\$ – horta Aug 23 '17 at 22:37
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Well no they are not synchronous in the definition, they are linked,you have a primary source, but you have delay and loop bandwidth issues,a PLL is always 'chasing' an error signal,and it is defined by the settling time of the loop? So in effect it is always playing 'catch up' , having cascaded feedback loops gives rise to a very unstable design, (audio? Oscillation), furthermore it is frequency dependent, as there will be filtering effects, so the loop bandwidth is ill defined? If you want more info, my email is: patrickhogan1969@gmail.com, i hope i can help a fellow out with a problem? Pat Hogan (Msc EPD)

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