4
\$\begingroup\$

I am working with an STM32F407xx microprocessor to analyze incoming signals generated by some hydrophones in a sonar system. At this point in time I am just reading through the datasheet and trying to figure out how the STM should be powered without all the peripherals for the sonar system attached (amplifier, filter, hydrophones, etc). I am having trouble reading the power supply layout provided shown in the diagram below.

[STM32F407xx Power Supply Scheme[1]

enter image description here

(Taken from the datasheet, Pg 77)

My specific questions are:

  1. What does 15 X 100nF actually mean? Why do I need FIFTEEN capacitors? Also how should these capacitors be connected? I know in note 1 underneath the diagram it says each power supply pair must be decoupled using filtering ceramic capacitors. But what does the notation 15 X 100nF + 1 X 4.7uF mean? Do I put 16 capacitors in parallel or what? I am so confused and I wasn't able to find anything on the internet related to the issue, probably because I don't know how to describe the issue that well. This same question applies to the other two highlighted capacitor sections that say 100 nF + 1uF. Again I assume they are in parallel but I'm not sure.
  2. What do dashed lines mean in a schematic diagram? I know the large rectangle with dashed lines is supposed to represent the physical boundaries of the STM but what do the dashed lines to the left of the ADC right by VREF+ and VREF- mean? I found some information online where people suggested that the dashed portions are just optional but I can't be sure.

I've been trying to figure this out forever so any help would be greatly appreciated!

\$\endgroup\$
7
\$\begingroup\$

To answer just your specific questions:

What does 15 X 100nF actually mean? Why do I need FIFTEEN capacitors .. what does the notation 15 X 100nF + 1 X 4.7uF mean?

They want you to have one 4.7 uF capacitor (aka "bulk capacitance", like a beefy storage tank) to main VDD rail, and then for each VDD pin they want you to put one 0.1 uF cap to GND near that IC pin. From the diagram, it seems like if you pick the package with the highest pin count (176 pins) it will have 15 VDD lines. The smaller packages would not have as many VDD pins so you can use less than 15 0.1 uF capacitors.

what do the dashed lines to the left of the ADC right by VREF+ and VREF- mean?

It means you can use either the VDD rail or an external VREF+ voltage as your ADC reference. If you use an external voltage reference, you should add a 0.1 uF cap in parallel with a 1 uF cap to filter it.

They put dashed lines to mean that you cannot obviously connect it to both at the same time. Pick one.

External VREF+ can be very helpful because VDD can bounce around and have noise which makes your ADC readings noisy. By using an external voltage reference IC, you can get a very accurate voltage and low noise because no other circuit loads it down. Also, these references are available in handy binary related numbers like 1.024 Volts, 2.048 Volts, 4.096 Volts, etc.

\$\endgroup\$
5
\$\begingroup\$

ST has a specific App Note, Getting Started with STM32F4xxxx MCU Hardware Development, which is a must-read when starting with this microcontroller. It gives details on power supply, clock management, reset control, and a few other important things.

This snippet from that document shows the answers to your questions. There is more information in the doc; I highly recommend you read through it.

![enter image description here

ST's datasheets are not the sum-total of knowledge needed to work with their microcontrollers. For any microcontroller family you should look to the Datasheet, the Reference Manual, and any number of Application Notes.

For the STM32F407 the Datasheet is here and the Reference Manual is here.

Many other App Notes can be found on ST's website. It can be helpful to read down the list and see what's available.

\$\endgroup\$
  • \$\begingroup\$ Well, you don't really have to read all their app notes, since this solution is very standard, as far as microcontroller layouts go. One big cap and then one 100nF decoupling cap per pin is what you would do per default, unless the manufacturer told you otherwise. \$\endgroup\$ – Lundin Aug 28 '17 at 14:18
  • 1
    \$\begingroup\$ A good way to learn these "defaults", of which there are many, is to read app notes :) \$\endgroup\$ – bitsmack Aug 28 '17 at 15:22

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.