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The CMOS version of a NAND gate has two NMOSes series on the bottom and two PMOSes in parallel on the top. We can replace the PMOSes with a resistor and the circuit works (alternative NAND). What are the differences between these two NANDS? Which one is better? Which one is practical? Why we use either of them?

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  • \$\begingroup\$ Why are you calling a technology almost 30 years obsolete "regular"? \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 26 '17 at 16:31
  • \$\begingroup\$ @IgnacioVazquez-Abrams I edited it and called it alternative. Now, do you have an answer? \$\endgroup\$ – Sus20200 Aug 26 '17 at 16:32
  • \$\begingroup\$ The answer is why the technology became obsolete in the first place: CMOS is faster. \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 26 '17 at 16:33
  • \$\begingroup\$ @IgnacioVazquez-Abrams Thanks. Can you explain more why is it faster? \$\endgroup\$ – Sus20200 Aug 26 '17 at 16:38
  • \$\begingroup\$ You can turn PMOSFETs off. \$\endgroup\$ – Ignacio Vazquez-Abrams Aug 26 '17 at 16:38
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There are two reasons, in my opinion: First, the CMOS Version can be built without resistors (obviously), which is a huge advantage in integrated circuits. So huge, that this is actually enough. Integrated resistors are gigantic in size, compared to the tiny transistors, which are needed for the NAND. Depending on the needed driver strength, these transistors can be really, really small. Second, the CMOS NAND uses no static power, since either the pull-up path or the pull-down path is of high impedace.

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The active pullup allows the risetime to be designed, thus Tpd(rise) can be quite small, indeed the same (or faster, if you spend the PMOS device area) than the Tpd(fall).

Larger devices have larger gate area, thus demanding more charge from whatever circuit generated the input waveform, but you can craft the pullup speed to be independent of falling edge speed. This is useful for make-before-break circuits.

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