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In my first high-speed PCB design, I have an LPDDR3 RAM and my PCB have 6 layers with the below sequence:

1-Signal

2-GND_Plane

3-Signal

4-Signal

5-VCC_Plane

6-Signal

the region between the SOC and RAM is totally covered by VCC-DRAM in the VCC_Plane layer. Considering all requirements of impedance controlling of all layers is truly fulfilled, My questions are:

  • Could I route my tracks in any of signal layers? aren't there any differences between referencing my tracks to GND or VCC?

  • Is there any special signal group for example differential pairs or data groups that I should exactly reference them to GND(routing only in layer 1 and 3) or to VCC(routing only in layer 4 and 6)?

  • If there isn't any difference between them, what is the fact behind that which makes VCC plane and GND plane behave the same in referencing signals?

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As long as GND and VCC are connected by several capacitors at both sending and receiving end of signal lines (as they should be, will be in high speed design), AND where the return current changes planes (which you should try to avoid) then it doesn't matter which plane the return current flows in. The return current is only interested in the AC impedance of the path.

Note that signals carried in layers 3 and 4 will be referenced to both return planes. You have the opportunity to choose core and pre-preg thicknesses so that the same widths on all layers could give you the same impedance, but if not, use different widths on 3 and 4 (which are offset stripline) to 1 and 6 (which are microstrip).

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  • \$\begingroup\$ And don't forget to add bypass caps in the area where high-speed signals change planes (which should be avoided). \$\endgroup\$ – Ale..chenski Aug 27 '17 at 3:55
  • \$\begingroup\$ @AliChen, damn, yes. \$\endgroup\$ – Neil_UK Aug 27 '17 at 6:19

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