2
\$\begingroup\$

I downloaded the symbol and model for the HC4046 Phase-Locked Loop chip from the Yahoo LTSpice group here:

https://groups.yahoo.com/neo/groups/LTspice/files/%20Lib/CD4046/Others%20CD4046/

(You will need an account and to be signed in to view this page).

The one I downloaded and installed was Full_feature_without_inhib.zip. I placed the HC4046.asy file in the default LTSpice sym folder, I put the HC4046.sub file in the sub folder, and put the HC4046.asc file (the subcircuit representing the HC4046) in the same directory as my project. In my project I added .include statements to include HC4046.sub as well as HC4046.asc. However, when I press the simulate button I get an error, Can't expand empty subcircuit: HC4046. I have scoured the net and have been unable to find even a mention of this error much less its cause or how to fix it. In what cases is this error produced, and is there a documented solution for it?

Contents of HC4046.sub:

*(MC74/HC)4046 Model
*author Paksutov Konstantin, aka [email protected]
*0.6.12.2010
.subckt HC4046 14 16 3 9 1 10 11 12 13 15 2 4 6 7 8
*SR-PFD-corrected
.subckt HC4046 14 16 3 9 1 10 11 12 13 15 2 4 6 7 8
S1 6 N003 7 8 SW
S2 8 7 7 8 SW
S3 7 N003 6 8 SW
S4 8 6 6 8 SW
C1 7 6 10p
B1 8 N003 I=I(R1)*36
B2 4 8 V=ddt(V(6,7))>0 ? 5 : 0 Tripdt=0.007u Tripdv=0.007m
R3 4 8 1G
R_by-pass-1 N002 8 2.7k
G1 8 N002 9 N002 TABLE(0.05, 0.001m) (0.31, 0.005m) (0.5, 0.011m) (2.29V, 
0.091m) (3V, 0.12m)
R_by-pass-2 N005 8 2.7k
G2 8 N005 16 N005 TABLE(0.05, 0.001m) (0.31, 0.005m) (0.5, 0.011m) (2.29V, 
0.091m) (3V, 0.12m)
B3 8 N003 I=I(R2)*90
A1 14 3 0 0 0 0 13 0 PHASEDET Vhigh={Vhigh1} Td={td1} ref={ref1}
R_by-pass-3 10 8 2.7k
G3 8 10 9 10 1
A2 0 14 0 3 0 0 2 0 XOR Vhigh={Vhigh1} TD=10n
A3 S R 0 0 0 0 15 0 SRFLOP Vhigh={Vhigh1} ref={ref1} Td={td1}
A4 16 0 N001 8 S 0 S 0 DFLOP Vhigh={Vhigh1} ref=0.1 Td={td1}
A6 16 0 N004 8 R 0 R 0 DFLOP Vhigh={Vhigh1} ref=0.1 Td={td1}
A10 14 0 0 0 0 N001 0 0 BUF Vhigh={Vhigh1} ref={ref1}
A11 3 0 0 0 0 N004 0 0 BUF Vhigh={Vhigh1} ref={ref1} Td={48*td1}
R1 N002 11 1n
R2 N005 12 1n
B4 1 8 V=inv(V(S))*5 Tripdt=0.007u Tripdv=0.007m
R4 1 8 1G
.ic V(6)=0.5
.params: Vhigh1=5 ref1=2.5 Td1=50n
.model SW SW(Ron=5 Roff=1Meg Vt=500m Vh=600m)
.ic V(15)=0 V(R)=0 V(S)=5
.ends HC4046

Contents of HC4046.asc:

Version 4
SHEET 1 4564 1120
WIRE 384 -432 352 -432
WIRE 464 -432 464 -480
WIRE 512 -432 464 -432
WIRE 592 -432 592 -464
WIRE 624 -432 592 -432
WIRE 800 -432 720 -432
WIRE -272 -416 -304 -416
WIRE -352 -400 -496 -400
WIRE 272 -384 272 -640
WIRE 288 -384 272 -384
WIRE 352 -384 352 -432
WIRE 368 -384 368 -464
WIRE 384 -384 368 -384
WIRE 592 -384 592 -432
WIRE 592 -384 544 -384
WIRE 624 -384 608 -384
WIRE 512 -368 512 -432
WIRE 592 -368 592 -384
WIRE 592 -368 512 -368
WIRE -480 -352 -496 -352
WIRE -448 -352 -480 -352
WIRE -352 -352 -368 -352
WIRE 464 -336 464 -384
WIRE -480 -320 -480 -352
WIRE -320 -320 -352 -352
WIRE -272 -320 -272 -416
WIRE -272 -320 -320 -320
WIRE 368 -288 368 -384
WIRE 384 -288 368 -288
WIRE 592 -288 592 -320
WIRE 592 -288 544 -288
WIRE 608 -288 608 -384
WIRE 608 -288 592 -288
WIRE -64 -272 -80 -272
WIRE 32 -272 16 -272
WIRE 48 -272 32 -272
WIRE 144 -272 128 -272
WIRE 592 -256 592 -288
WIRE 592 -256 464 -256
WIRE 240 -240 240 -640
WIRE 304 -240 240 -240
WIRE 384 -240 368 -240
WIRE 32 -192 32 -272
WIRE 32 -192 -112 -192
WIRE 176 -192 32 -192
WIRE 464 -192 464 -256
WIRE -272 -176 -304 -176
WIRE -112 -176 -112 -192
WIRE 176 -176 176 -192
WIRE 608 -176 592 -176
WIRE 800 -176 672 -176
WIRE -352 -160 -496 -160
WIRE 608 -144 576 -144
WIRE -480 -112 -496 -112
WIRE -448 -112 -480 -112
WIRE -352 -112 -368 -112
WIRE -480 -80 -480 -112
WIRE -320 -80 -352 -112
WIRE -272 -80 -272 -176
WIRE -272 -80 -320 -80
WIRE -112 -80 -112 -96
WIRE 0 -80 -112 -80
WIRE 176 -80 176 -96
WIRE 176 -80 64 -80
WIRE -32 -64 -112 -80
WIRE 96 -64 176 -80
WIRE 272 -64 272 -384
WIRE 608 -64 272 -64
WIRE -112 -48 -112 -80
WIRE 176 -48 176 -80
WIRE 784 -48 736 -48
WIRE 240 -32 240 -240
WIRE 608 -32 240 -32
WIRE -160 32 -160 16
WIRE -112 32 -160 32
WIRE 32 32 -112 32
WIRE 176 32 32 32
WIRE 224 32 224 16
WIRE 224 32 176 32
WIRE -272 48 -304 48
WIRE 32 48 32 32
WIRE -352 64 -416 64
WIRE -480 112 -496 112
WIRE -352 112 -480 112
WIRE 640 128 592 128
WIRE 768 128 640 128
WIRE -480 144 -480 112
WIRE -320 144 -352 112
WIRE -272 144 -272 48
WIRE -272 144 -320 144
WIRE 416 144 400 144
WIRE 592 144 592 128
WIRE 336 192 320 192
WIRE 416 192 416 144
WIRE 640 224 640 208
WIRE -32 304 -32 -64
WIRE 96 304 96 -64
WIRE 176 304 176 224
WIRE 416 320 416 192
FLAG -32 304 6
IOPIN -32 304 BiDir
FLAG 96 304 7
IOPIN 96 304 BiDir
FLAG -160 -160 7
FLAG 224 -32 7
FLAG -160 -32 6
FLAG 224 -160 6
FLAG 768 128 4
IOPIN 768 128 Out
FLAG -496 -352 11
IOPIN -496 -352 Out
FLAG -496 -160 16
IOPIN -496 -160 In
FLAG -496 -112 12
IOPIN -496 -112 Out
FLAG 272 -640 14
IOPIN 272 -640 In
FLAG 240 -640 3
IOPIN 240 -640 In
FLAG -496 -400 9
IOPIN -496 -400 In
FLAG -416 64 9
FLAG -496 112 10
IOPIN -496 112 Out
FLAG 592 -176 14
FLAG 576 -144 3
FLAG 800 -176 2
IOPIN 800 -176 Out
FLAG 784 -48 13
IOPIN 784 -48 Out
FLAG 368 -464 16
FLAG 800 -432 15
IOPIN 800 -432 Out
FLAG 592 -320 R
FLAG 592 -464 S
FLAG -304 -336 COM
FLAG -272 -240 COM
FLAG -304 -96 COM
FLAG -272 0 COM
FLAG -304 128 COM
FLAG -272 224 COM
FLAG -80 -272 COM
FLAG 144 -272 COM
FLAG 224 -112 COM
FLAG -160 -112 COM
FLAG 32 48 COM
FLAG 464 -384 COM
FLAG 592 224 COM
FLAG 640 224 COM
FLAG 176 224 COM
FLAG 176 304 8
IOPIN 176 304 BiDir
FLAG 416 320 1
IOPIN 416 320 Out
FLAG 320 144 COM
FLAG 320 192 COM
SYMBOL sw -112 -80 M180
SYMATTR InstName S1
SYMBOL sw 176 48 R180
SYMATTR InstName S2
SYMBOL sw 176 -80 R180
SYMATTR InstName S3
SYMBOL sw -112 48 M180
SYMATTR InstName S4
SYMBOL cap 64 -96 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C1
SYMATTR Value 10p
SYMBOL bi2 16 -272 M270
WINDOW 3 -32 40 VBottom 0
WINDOW 0 32 40 VTop 0
SYMATTR Value I=I(R1)*36
SYMATTR InstName B1
SYMBOL bv 592 128 M0
WINDOW 3 24 104 Invisible 0
SYMATTR Value V=ddt(V(6,7))>0 ? 5 : 0
SYMATTR InstName B2
SYMATTR Value2 Tripdt=0.007u Tripdv=0.007m
SYMBOL res 624 112 R0
SYMATTR InstName R3
SYMATTR Value 1G
SYMBOL res -288 -336 R0
SYMATTR InstName R_by-pass-1
SYMATTR Value 2.7k
SYMBOL g -304 -432 R0
WINDOW 3 -475 544 Invisible 0
WINDOW 0 -37 9 Left 0
SYMATTR Value TABLE(0.05, 0.001m) (0.31, 0.005m) (0.5, 0.011m) (2.29V, 0.091m) (3V, 0.12m)
SYMATTR InstName G1
SYMBOL res -288 -96 R0
SYMATTR InstName R_by-pass-2
SYMATTR Value 2.7k
SYMBOL g -304 -192 R0
WINDOW 3 -475 544 Invisible 0
WINDOW 0 -41 9 Left 0
SYMATTR Value TABLE(0.05, 0.001m) (0.31, 0.005m) (0.5, 0.011m) (2.29V, 0.091m) (3V, 0.12m)
SYMATTR InstName G2
SYMBOL bi2 48 -272 M90
WINDOW 3 32 40 VTop 0
WINDOW 0 -32 40 VBottom 0
SYMATTR Value I=I(R2)*90
SYMATTR InstName B3
SYMBOL Digital\\phidet 640 -48 R0
WINDOW 3 0 64 Invisible 0
SYMATTR Value Vhigh={Vhigh1}
SYMATTR InstName A1
SYMATTR Value2 Td={td1} ref={ref1}
SYMBOL res -288 128 R0
SYMATTR InstName R_by-pass-3
SYMATTR Value 2.7k
SYMBOL g -304 32 R0
WINDOW 3 -475 544 Invisible 0
WINDOW 0 -25 14 Left 0
SYMATTR Value 1
SYMATTR InstName G3
SYMBOL Digital\\xor 656 -224 R0
WINDOW 3 0 0 Invisible 0
SYMATTR Value Vhigh={Vhigh1}
SYMATTR InstName A2
SYMATTR Value2 TD=10n
SYMBOL Digital\\srflop 672 -480 R0
WINDOW 3 -40 152 Invisible 0
SYMATTR Value Vhigh={Vhigh1} ref={ref1}
SYMATTR InstName A3
SYMATTR Value2 Td={td1}
SYMBOL Digital\\dflop 464 -336 M180
WINDOW 3 8 168 Invisible 0
WINDOW 0 8 -16 Invisible 0
SYMATTR Value Vhigh={Vhigh1} ref=0.1
SYMATTR InstName A4
SYMATTR Value2 Td={td1}
SYMBOL Digital\\dflop 464 -336 R0
WINDOW 3 8 168 Invisible 0
WINDOW 0 8 -16 Invisible 0
SYMATTR Value Vhigh={Vhigh1} ref=0.1
SYMATTR InstName A6
SYMATTR Value2 Td={td1}
SYMBOL Digital\\inv 288 -448 R0
WINDOW 3 8 104 Invisible 0
SYMATTR Value Vhigh={Vhigh1} ref={ref1}
SYMATTR InstName A10
SYMBOL Digital\\inv 304 -304 R0
WINDOW 3 8 104 Invisible 0
SYMATTR Value Vhigh={Vhigh1} ref={ref1}
SYMATTR InstName A11
SYMATTR Value2 Td={48*td1}
SYMBOL res -352 -368 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 1n
SYMBOL res -352 -128 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 1n
SYMBOL bv 416 144 M270
WINDOW 3 82 56 VBottom 0
WINDOW 0 32 56 VTop 0
SYMATTR Value V=inv(V(S))*5
SYMATTR InstName B4
SYMATTR Value2 Tripdt=0.007u Tripdv=0.007m
SYMBOL res 432 176 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R4
SYMATTR Value 1G
TEXT -480 -536 Left 0 !.ic V(6)=0.5\n.params: Vhigh1=5 ref1=2.5 Td1=50n\n.model SW SW(Ron=5 Roff=1Meg Vt=500m Vh=600m)
TEXT -632 -432 Left 0 ;9 --- VCO_in
TEXT 784 104 Left 0 ;4 --VCO_out
TEXT 608 24 Left 0 ;13 --Phase_COMP II OUT
TEXT 432 -16 Left 0 ;3 --COMP_in
TEXT -552 -200 Left 0 ;VCC
TEXT 400 -88 Left 0 ;14 --(VCO)SIG_in
TEXT -600 80 Left 0 ;DEM_OUT
TEXT -296 400 Left 0 ;author Paksutov Konstantin, Ulyanovsk State University, aka [email protected]
TEXT 448 -528 Left 0 !.ic V(15)=0 V(R)=0 V(S)=5
RECTANGLE Normal 752 256 -480 -608

Contents of my project file:

Version 4
SHEET 1 880 680
WIRE -304 -144 -320 -144
WIRE -288 -144 -304 -144
WIRE -176 -144 -192 -144
WIRE -160 -144 -176 -144
WIRE -320 -112 -320 -144
WIRE -192 -112 -192 -144
WIRE -320 0 -320 -32
WIRE -192 0 -192 -32
WIRE -80 80 -96 80
WIRE -32 80 -80 80
WIRE 208 80 208 32
WIRE 208 80 160 80
WIRE -352 112 -368 112
WIRE -256 112 -272 112
WIRE -240 112 -256 112
WIRE -32 112 -128 112
WIRE -256 144 -256 112
WIRE -64 144 -96 144
WIRE -32 144 -64 144
WIRE 208 144 160 144
WIRE 480 144 208 144
WIRE -32 176 -208 176
WIRE -480 208 -480 112
WIRE -432 208 -480 208
WIRE -400 208 -432 208
WIRE -32 208 -160 208
WIRE -256 224 -256 208
WIRE -208 224 -208 176
WIRE -160 224 -160 208
WIRE -32 240 -112 240
WIRE 240 240 160 240
WIRE 336 240 320 240
WIRE 368 240 336 240
WIRE 400 240 368 240
WIRE -32 272 -80 272
WIRE 336 272 336 240
WIRE -80 304 -80 272
WIRE -80 304 -112 304
WIRE -32 304 -64 304
WIRE -208 336 -208 304
WIRE -160 336 -160 304
WIRE -64 336 -64 304
WIRE 336 352 336 336
FLAG -64 336 0
FLAG -320 0 0
FLAG -304 -144 +5V
FLAG 208 32 +5V
FLAG -192 0 0
FLAG -176 -144 FB
FLAG -80 80 FB
FLAG 336 352 0
FLAG -64 144 VCOi
FLAG 368 240 VCOi
FLAG 208 144 VCOo
FLAG -432 208 VCOo
FLAG -256 224 0
FLAG -208 336 0
FLAG -160 336 0
SYMBOL HC4046 32 256 R0
SYMATTR InstName X1
SYMATTR SpiceModel ..\sub\HC4046.sub
SYMBOL voltage -320 -128 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -192 -128 R0
WINDOW 3 64 16 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value PULSE(0 5 0 10n 10n 4.15u 8.3u)
SYMATTR InstName V2
SYMBOL res 336 224 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1
SYMATTR Value 13.3k
SYMBOL cap 320 272 R0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL 74HCT\\74hct14 -192 64 R0
SYMATTR InstName U1
SYMBOL 74HCT\\74hct14 -432 64 R0
SYMATTR InstName U2
SYMBOL res -256 96 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100
SYMBOL cap -272 144 R0
WINDOW 0 -35 30 Left 2
WINDOW 3 -32 56 Left 2
SYMATTR InstName C2
SYMATTR Value 1n
SYMBOL cap -128 240 R0
WINDOW 0 29 -16 Left 2
WINDOW 3 29 16 Left 2
SYMATTR InstName C3
SYMATTR Value 10n
SYMBOL res -176 208 R0
WINDOW 0 23 84 Left 2
WINDOW 3 26 110 Left 2
SYMATTR InstName R3
SYMATTR Value 220k
SYMBOL res -224 208 R0
WINDOW 0 -49 78 Left 2
WINDOW 3 -54 104 Left 2
SYMATTR InstName R4
SYMATTR Value 22k
TEXT -352 488 Left 2 !.tran 0 32u 0 1u
TEXT -352 416 Left 2 !.include HC4046.sub
TEXT -352 448 Left 2 !.include HC4046.asc

Contents of HC4046.sym:

Version 4
SymbolType CELL
RECTANGLE Normal 128 64 -64 -192
TEXT 35 19 VLeft 2 (MC74/HC)4046
WINDOW 0 31 -195 Bottom 2
SYMATTR Description Fase Prequency Detector with VCO
SYMATTR Value2 HC4046
SYMATTR Value HC4046
SYMATTR SpiceModel ..\sym\Mylib\HC4046.sub
PIN -64 -176 LEFT 8
PINATTR PinName 14
PINATTR SpiceOrder 1
PIN 128 -176 RIGHT 8
PINATTR PinName 16
PINATTR SpiceOrder 2
PIN -64 -144 LEFT 8
PINATTR PinName 3
PINATTR SpiceOrder 3
PIN -64 -112 LEFT 8
PINATTR PinName 9
PINATTR SpiceOrder 4
PIN 128 -80 RIGHT 8
PINATTR PinName 1
PINATTR SpiceOrder 5
PIN 128 48 RIGHT 8
PINATTR PinName 10
PINATTR SpiceOrder 6
PIN -64 -80 LEFT 8
PINATTR PinName 11
PINATTR SpiceOrder 7
PIN -64 -48 LEFT 8
PINATTR PinName 12
PINATTR SpiceOrder 8
PIN 128 -16 RIGHT 8
PINATTR PinName 13
PINATTR SpiceOrder 9
PIN 128 16 RIGHT 8
PINATTR PinName 15
PINATTR SpiceOrder 10
PIN 128 -48 RIGHT 8
PINATTR PinName 2
PINATTR SpiceOrder 11
PIN 128 -112 RIGHT 8
PINATTR PinName 4
PINATTR SpiceOrder 12
PIN -64 -16 LEFT 8
PINATTR PinName 6
PINATTR SpiceOrder 13
PIN -64 16 LEFT 8
PINATTR PinName 7
PINATTR SpiceOrder 14
PIN -64 48 LEFT 8
PINATTR PinName 8
PINATTR SpiceOrder 15
\$\endgroup\$
17
  • 1
    \$\begingroup\$ Can you post the contents of the .asc and .sub files here? \$\endgroup\$
    – ThreePhaseEel
    Commented Aug 27, 2017 at 2:49
  • \$\begingroup\$ I found "Examples\LtSpicePlus\x046\Paksutov_Models\74HC4046\Full_feature_without_inhib" which I suspect is the same as yours. I put the .asy and .sub files in the same folders you did, then loaded the example schematic "Full_No_inh_test.asc" which simulated fine. In this schematic the HC4046 is added as a component (which is listed in lib\sim when selecting a component symbol). \$\endgroup\$
    – Bruce Abbott
    Commented Aug 27, 2017 at 5:36
  • \$\begingroup\$ You shouldn't mess with the default installation. After extraction, just run the schematic as it is. Ltspice will first search for .asy and .sub files inside the current directory. Furthermore, if you used XVII, then the symbols and subcircuits that are used reside inside your My Documents/LTspiceXVII folder, rather than Program Files. \$\endgroup\$
    – a concerned citizen
    Commented Aug 27, 2017 at 6:46
  • \$\begingroup\$ @ThreePhaseEel Done \$\endgroup\$
    – DerStrom8
    Commented Aug 27, 2017 at 12:30
  • \$\begingroup\$ @BruceAbbott Yep, that's what I did too. I went to the component menu to add the HC4046 to the schematic, and I used the .include statements to pull in the model and subcircuit. \$\endgroup\$
    – DerStrom8
    Commented Aug 27, 2017 at 12:31

1 Answer 1

Reset to default
2
\$\begingroup\$

This error message is caused by multiple .subckt lines in the "HC4046.sub" file:-

.subckt HC4046 14 16 3 9 1 10 11 12 13 15 2 4 6 7 8
*SR-PFD-corrected
.subckt HC4046 14 16 3 9 1 10 11 12 13 15 2 4 6 7 8
S1 6 N003 7 8 SW
S2 8 7 7 8 SW
...

The first instance is 'empty', ie. doesn't describe a circuit, while the second one does. removing either line stops the error from occurring.

\$\endgroup\$
2
  • \$\begingroup\$ I tried removing the first one already and it did not solve the problem. \$\endgroup\$
    – DerStrom8
    Commented Aug 29, 2017 at 19:55
  • \$\begingroup\$ It certainly did the trick for me (even on a clean install of LTspice) and makes sense. Did you still get the same error, or a different one? Are you sure you edited the correct file? Try putting all 4 files into the same folder, and remove any paths to other locations. \$\endgroup\$
    – Bruce Abbott
    Commented Aug 29, 2017 at 20:37

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