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I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. Also the PRN pin confuse me. I have included a link to the altera documentation that I have been using so far.

http://quartushelp.altera.com/14.1/mergedProjects/hdl/prim/prim_pu_pinstub_names.htm

enter image description here

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    \$\begingroup\$ Why do you need a primitive? Can't you write it as portable, generic VHDL or Verilog code? \$\endgroup\$ – Paebbels Aug 27 '17 at 9:00
  • \$\begingroup\$ I am pretty sure that will be a right solution. But at this point I am trying to map features between the two IDEs for educational reasons. \$\endgroup\$ – artificer Aug 27 '17 at 19:29
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Newer versions of Quartus have wrappers for different basic flip-flop types. A list of all primitives can be found here: Primitive List for Quartus 15

Here is the DFFE component:

COMPONENT DFFE
  PORT (
    d    : IN  STD_LOGIC;   -- Data input
    clk  : IN  STD_LOGIC;   -- Clock
    clrn : IN  STD_LOGIC;   -- Clear (Reset, low-active)
    prn  : IN  STD_LOGIC;   -- Preset (low-active)
    ena  : IN  STD_LOGIC;   -- (Clock) Enable
    q    : OUT STD_LOGIC    -- Data output
  );
END COMPONENT;

Source: http://quartushelp.altera.com/15.0/mergedProjects/hdl/prim/prim_file_dffe.htm


Outdated Altera documentation:

There is the Quartus Low Level Primitive Guide.

Here is the basic flip-flop cell:

COMPONENT DFFEAS
  PORT (
    d      : IN  STD_LOGIC;
    clk    : IN  STD_LOGIC;
    clrn   : IN  STD_LOGIC;
    prn    : IN  STD_LOGIC;
    ena    : IN  STD_LOGIC;
    asdata : IN  STD_LOGIC;
    aload  : IN  STD_LOGIC;
    sclr   : IN  STD_LOGIC;
    sload  : IN  STD_LOGIC;
    q      : OUT STD_LOGIC
  );
END COMPONENT; 

Quartus has only one primitive, whereas Xilinx offers different wrappers for the same primitive.

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