I am trying to create a test board for Apex MP38. I am following their own evaluation kit design and noticed there are 2 clamping diodes between the OpAmp's output and the positive and negative rails:

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My question is, why they have put this divides? what will they do? what is the effect of their presence in the overall output of the opamp? Because in the datasheet the typical application DOES NOT have these diodes:

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Further more, the evaluation kit does not list the part number of these diodes. Judging from their size, I think they are DOA201AD...something like 1n5408 maybe? Silicon or Schotkey? any ideas?


The role of the diodes is to clamp voltage spikes generated by an inductive load to the supplies.

Your Apex opamp is not an IC, it is made from discrete components soldered onto a metal core PCB. Thus it will not latch-up...

Also, the onboard output transistors already contain beefy clamping diodes because they are MOSFETs.

So, adding extra diodes seems a bit weird, unless they do something the FET body diodes don't.

My first hypothesis would be that this eval board can be used with other power opamps of the same manufacturer, and some of them would have output BJTs instead of FETs, and BJTs would need diodes if used in inductive loads. But in this case, why wouldn't the diodes be on the opamps themselves ?... And the document mentions the eval board being compatible with two power opamps, which both use FETs.

The plot thickens!

Now, on page 3 the eval kit manual says:

Mount diodes at D1 and D2 and transorbs at D3 and D4 on the “component side” of the board (none supplied) as needed by your application. See Application Note 1 paragraphs 4.3 and 9.1.

...and the appnote says:

Although most power amplifiers have some kind of internal flyback protection diodes, these internal diodes should not be counted on to protect the amplifier against sustained high frequency, high energy kickback pulses. Many of these diodes are intrinsic “epi” diodes that occur as a result of the manufacture of the power darlington output transistor. Epi diodes generally have slow reverse recovery times and may have large forward voltage drops. Under sustained high energy flyback conditions, high speed, fast reverse recovery diodes should be used from the output of the op amps to the supplies to augment the internal diodes. See Figure 16. These fast recovery diodes should have reverse recovery times of less than 100 nanoseconds and for very high frequency energy should be under 20 nanoseconds.

So here's your answer: some loads are nasty enough that the FET body diodes can't deal with them, because FET body diodes usually have rather bad specs, and a dedicated diode can be made much better.

  • \$\begingroup\$ Thanks for the great insight! I got the idea very well...I'll add the footprint to my own design for diodes just in case :) \$\endgroup\$ – Sean87 Aug 27 '17 at 19:22
  • \$\begingroup\$ I promised to put the footprints for diodes...and they are there :D electronics.stackexchange.com/questions/330465/… But now I have a bigger problem :( \$\endgroup\$ – Sean87 Sep 21 '17 at 20:10

These two diodes are there to safely clamp the output voltage excursion within safe limits for the IC: if for any reason, e.g. if you drive an inductive load, you force \$V_{out}\$ to rise and potentially exceed the component \$V_{cc}\$, a so-called latch-up can be induced and destroy the part (especially if the supply rail is not current-limited). Latch-up occurs because you fire a parasitic SCR hidden in the various layers the IC is made of. With the upper-side diode, the inductive current will circulate through the diode, safely keeping away from the power op amp output power stage. Same for the low-side diode which prevents the output from swinging below ground. Having an integrated circuit pin biased below ground can induce so-called substrate injection and may engender an erratic behavior (you inject carriers in the substrate). Without entering into the details, some of these pins are ESD-protected (protection against static discharges) and if you forward-bias some of the internal Zener diodes located in the ESD structures by applying a negative bias (you have to inject current over some period of time), substrate injection can occur with all nasty consequences (erratic behavior to IC destruction by latch-up). This is why most of the data-sheets mention that any pin voltage excursion should be limited between -0.3 V to \$V_{cc}+0.6\;V\$. For high-voltage ICs this is another story, but usually this is what is stated. By using Schottky diodes for these two elements, you should be safe.

  • \$\begingroup\$ actually the amplifier in question is made of discrete parts, so it won't latchup, I found the answer in the docs :) it's about recovery time. \$\endgroup\$ – peufeu Aug 27 '17 at 18:40
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    \$\begingroup\$ No problem, at least I've tried! : ) \$\endgroup\$ – Verbal Kint Aug 27 '17 at 20:33

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