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I have a question about the DDR4 trace routing on the server main board.

For clock and DQS signals, are they both considered differential signals?

I checked the Intel PDG; it shows that two specs for the impedance control on these signals.

In one table, it specifies the single-ended impedance spec. In another table, it defines the trace spacing between P/N trace. Does anyone know why the spec defines the single-ended impedance for the differential pair? Why not just define the differential impedance?

I also saw a spec for clock and DQS in another layout guideline. It says that the trace of these signals should be routed as a "pseudo differential pair", which means that we should first consider one trace as single-ended (here the spec defines 50 Ohm), and then try to meet the spacing as in the spec.

Again, why should we define the single-ended impedance for a differential pair?

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  • \$\begingroup\$ Probably something to do with termination < hand waving / > \$\endgroup\$ – vicatcu Aug 28 '17 at 16:40
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DDR4 uses POD (Pseudo Open Drain, see picture below) signaling with:

  • strong LOW level (0) = high power consumption,
  • weaker HIGH level (1) = low (near to zero) power consumption.

DDR4 – Pseudo Open Drain

(example from Micron's TN-40-40, Figure 11)

To save power, the paired signals DQS_t and DQS_c are both kept HIGH during bus idles and commands issuing. Therefore, during such times the paired signals act as single-ended lines.

To transfer data, the paired signals DQS_t and DQS_c are pre-driven oppositely during a READ/WRITE preamble, then changed oppositely during data transmission cycles, and then post-driven again oppositely and then both HI during a READ/WRITE postamble (see picture below). Therefore, during such times the paired signals act as a differential line.

preamble and postamble

(example from JEDEC Standard No. 79-4, Section 4.21.2)

Based on this, DDR4 paired signals should be routed so complex: each signal of a pair should be routed as a single-ended, controlled-impedance transmission line as well as the whole pair should be routed as a differential, controlled-impedance transmission line.


P.S. Strongly speaking, JEDEC Standard for DDR4 does not introduce DQS's clearly as "differential pairs", instead, it states the following in short (that "in full" is described in it later):

The data strobe DQS_t, DQSL_t and DQSU_t are paired with differential signals DQS_c, DQSL_c, and DQSU_c, respectively, to provide differential pair signaling to the system during reads and writes. DDR4 SDRAM supports differential data strobe only and does not support single-ended.

(text from JEDEC Standard No. 79-4, Section 2.6)

Compare that with the introduction of CK's signals in the same document:

CK_t and CK_c are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK_t and negative edge of CK_c.

(text from JEDEC Standard No. 79-4, Section 2.6)

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