Seriously, I mean the "logic": not AND and OR gates, but the intuition behind it.
This will be an investment of time for whoever answers, so I understand those who don't want to! I'm using this half as a way to get my thoughts in order, but to also get valuable insight from others on this website.
Here is my situation:
I have a CPU that is hardwired to a Kintex-7 FPGA. From the CPU, I am using "Xilinx System Generator" (an add-on to Simulink) to program the FPGA. From the FPGA, we have a 6 RX fiber optic cables and 6 TX fiber optic cables.
In our current setup, we are using all 6 of the TX cables in order to send gate signals to a three-phase half-bridge converter. Obviously, using 6 cables to drive 6 gate signals isn't a very elegant solution.
What I would like to do is remove the need for 5 of the cables. My plan is to take all of the gate signal information (which should only be 6 bits at a time), and feed it to a "Lattice" FPGA (I think Lattice is one of the major players in the FPGA market, and their products are quite cheap on Digikey).
My idea is as so: on the Lattice, have a counter and an incrementer. On the single fiber optic cable, the first bit would be a clock pulse: this first bit would reset the counter and incrementer on the Lattice FPGA. The following 12 bits would be gates 1-12. By resetting the counter, I think it would be easy to tell which gate signal to go where: the first clock cycle following the reset would trigger the first gate, the second would trigger the second, and so on.
As I was writing this, I realized this isn't going to be trivial: assuring that the Kintex-7 FPGA and the Lattice FPGA are phase- and clock-locked may not be a simple task. I believe this is the area that I need the most help in. Once I can get the FPGA's clocks to be locked together, I believe this will be an easy task.
Any opinions on how I can accomplish this? Having 6 TX/RX fiber optic cables doing the job of 1 cable makes me cringe; I know I can