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I've got a lot of experience with rather "low-level" electronics (resistor networks, passive filters, basic op-amp circuits) and some experience with higher-level stuff like micro-controllers, but I am currently struggling with learning the bits in between. As such, apologies if this question is daft or an obvious duplicate but here goes.

I have been working on a circuit which a colleague of mine designed which includes an LTC6655 2.5V voltage reference. In the circuit, and on the datasheet, the device calls for a 10uF cap to be placed on its outputs, but it doesn't say why. Since I was waiting for a delivery of 10uF caps and only had smaller ones, I foolishly assumed it was just there for line smoothing/filtering and decided that it wouldn't make a difference to the testing if I just left that part out until the delivery arrived.

Of course when I powered up the circuit, the reference was only putting out 1.75V instead of 2.5V. After checking all the inputs and outputs thoroughly, and the load parameters, I was stumped and went back to my colleague who pointed out the missing capacitor as being needed "for stability". I skeptically installed the needed part (which just arrived) and immediately the thing worked as expected.

Would anyone be willing to point me to a text to explain what that capacitor is doing, or even to explain it to me themselves? I would greatly appreciate it.

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    \$\begingroup\$ Page 11 of the spec sheet goes into a lot of wordage about the load cap... cds.linear.com/docs/en/datasheet/6655ff.pdf Perhaps you can figure it out from that, I'm thinking the ESR of whatever you originally used may have been too high. \$\endgroup\$ – Trevor_G Aug 29 '17 at 17:31
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    \$\begingroup\$ This link provides a lot of very specific detail for you, precisely targeted at your question: ti.com/lit/wp/snoa842/snoa842.pdf Start on the bottom of page 5, under Linear Regulators. \$\endgroup\$ – jonk Aug 29 '17 at 17:36
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    \$\begingroup\$ Without the capacitor, it was probably putting out rail to rail oscillations, whose mean value just happened to be 1.7V. \$\endgroup\$ – Brian Drummond Aug 29 '17 at 18:22
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The reference has a low dropout, so as you can see on the internal schematic (datasheet page 10) it is implemented as a bandgap reference followed by a rail to rail buffer opamp.

Notice the polarity of the output devices, the PMOS is on top and the NMOS on the bottom, which is a rail to rail output stage.

Both transistors behave as controlled current sources. It is possible to make such an opamp stable without a capacitor on the output, like most opamps, but here it is expected that the reference will have a cap on the output.

Making such a rail to rail output stage (which is very similar to a LDO) stable both with and without capacitance is difficult. Since the output transistors are controlled current sources, the output cap's value controls the open loop gain. Also its ESR adds a zero.

So, the designers settled on a particular value of capacitance and tuned the circuit for it. If you look at "output noise spectrum" page 10 on the bottom, you'll see that 10µF is optimum... this isn't a magic value, simply the designer tuned the circuit for that.

Now, datasheet page 11 gives hints on capacitor selection, so you should also read it...

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    \$\begingroup\$ +1 for specifically mentioning LDO, which is probably central to the question. \$\endgroup\$ – jonk Aug 29 '17 at 17:38
  • \$\begingroup\$ Mea culpa- I skimmed past the bit on page 11 without properly reading it. But it still remains unclear to me exactly how how the lack of capacitor introduces a voltage offset. Apologies if I'm just being dense (which based on other respondents' approaches, it seems I am)... \$\endgroup\$ – Magic_Matt_Man Aug 29 '17 at 18:11
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    \$\begingroup\$ @Magic_Matt_Man, Re: voltage offset, look at it with a 'scope, it may be oscillating. \$\endgroup\$ – George Herold Aug 29 '17 at 18:17
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    \$\begingroup\$ The "voltage offset" is due to your multimeter measuring something that may or may not be close to the average of the oscillating voltage... depending on frequency, multimeter, waveshape error could be small or substantial, who knows? Better use a scope. \$\endgroup\$ – peufeu Aug 29 '17 at 18:26
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This has to do with loop stability.

I won't go into the details of the Barkhausen stability criterion as I think it would go to far for this, but perhaps an analogy can explain what is going on. This will involve a lot of "handwavey" terms, but I'm worried if I go into the mathematics, it will be too hard to understand for someone new to the concept.

Inside the voltage reference, there will be some kind of buffer circuit. This is some form of opamp that has to try and set the output to the same value as the input. This way, you don't draw current from the actual voltage reference which can improve the performance.

Now imagine the following: The opamp has some form of feedback so it can compare the current output voltage with the reference voltage. The thing is that there is some form of lag (this is the phase response of the circuit) between it measuring the input, and it changing the output.

Let's say that the output is a bit too small. The opamp notices this difference and tries to increase the output voltage. It does so, and now notices that the output is at the same level as the input, so it tries to stop this increase in level. However, as I already said, there is some delay between its input measurement and the change in ouput - in other words, the output will go too high because the opamp can't stop fast enough. Now the opamp notices that the output is too high, so it tries to push it back down. Again, it starts doing so, but once it's just right, it will be too late and go to low. This keeps on happening over and over again - it's like there is a wave on the output! In other words, you don't have a nice stable voltage, but you have a swaying voltage that constantly over and undershoots! This is what we call loop instability.

So, where does that capacitor come in? The key is that the speed the opamp can push it's output up and down. If you add capacitance, it needs to work harder to push it's output one way or another. This means that there will be no overshoot (or at least it will slowly die out). The opamp can now respond more rapidly than it can change the output, so it will no longer constantly be lagging behind having the output swing above and below the reference voltage.

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  • \$\begingroup\$ Thanks for the explanation. I already understand how oscillations come about in a feedback system, and I understand what stability is. What I don't understand is why I was reading a simple voltage drop. Is it just that the output was actually oscillating fast and the DMM was just reading an RMS value? Is this what you're getting at in your last paragraph? "it will no longer constantly be lagging behind having the output swing above and below the reference voltage." \$\endgroup\$ – Magic_Matt_Man Aug 29 '17 at 18:05
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    \$\begingroup\$ I wasn't sure what you did or didn't understand, hence I explained the source of instability. What voltage were you supplying your circuit with? It's very possible your opamp was oscillating and hitting it's rails in doing so. 1.53V could then be an average value. \$\endgroup\$ – Joren Vaes Aug 29 '17 at 18:17
  • \$\begingroup\$ Yes that's great, thanks very much. I think that is what was happening. \$\endgroup\$ – Magic_Matt_Man Aug 30 '17 at 11:44
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A reference like your LT part or an LDO is a control system, measuring the output and comparing it with a reference to try to keep the output at the desired voltage. I.e. it uses feedback.

Any time you have a feedback control system, there exists the potential for instability. For example if there's enough delay in feeding back the output signal such that by the time the correction arrives it actually reinforces the error you will get oscillation.

In more rigorous terms you have to look at the open-loop transfer function, and if there's -180 degrees of phase shift when the gain crosses 0dB your loop will be unstable. Your working capacitor is affecting the shape of the open loop gain such that there is sufficient "phase margin". (The phase difference to -180 degrees when the gain crosses 0dB). The ESR of your cap along with the capacitance create a zero, which boosts the phase and may be the reason for the added stability.

You can find a lot of information on the web if you Google "control theory".

For example: Classical Control Theory

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    \$\begingroup\$ +1 for specifically mentioning LDO, which is probably central to the question. \$\endgroup\$ – jonk Aug 29 '17 at 17:38
  • \$\begingroup\$ I understand some control theory, I understand how oscillations come about in a feedback system, and I understand what "stability" is. What I don't understand is why I was reading a simple voltage drop. Is it just that the output was actually oscillating fast and the DMM was just reading an RMS value? \$\endgroup\$ – Magic_Matt_Man Aug 29 '17 at 18:03
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    \$\begingroup\$ Hard to say what the DMM was reading, but it could certainly read an oscillating signal as some DC value (Maybe RMS if it's a true-RMS meter and the signal was withing the BW of the RMS circuit.) Of course a 'scope is the way to tell for sure. \$\endgroup\$ – John D Aug 29 '17 at 18:37
  • \$\begingroup\$ Yes, thanks for the suggestion. Although I understand how oscillations can come about in general, I hadn't made the connection that they might be causing my difficulties in this particular case, hence I didn't think of using a scope, just a DC DMM. I've checked it with a scope and there are indeed oscillations (even with the capacitor in place) so there is something else wrong somewhere... Time for another bug hunt! \$\endgroup\$ – Magic_Matt_Man Aug 30 '17 at 11:42
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In the circuit, and on the datasheet, the device calls for a 10uF cap to be placed on its outputs, but it doesn't say why

The data sheet says: -

An output capacitor with a value between 2.7μF and 100μF is also required

The output capacitor has a direct effect on the stability, turn-on time and settling behavior. Choose a capacitor with low ESR to insure stability. Resistance in series with the output capacitor (ESR) introduces a zero in the output buffer transfer function and could cause instability. The 2.7μF to 100μF range includes several types of capacitors that are readily available as through-hole and surface mount components. It is recommended to keep ESR less than or equal to 0.1Ω. Capacitance and ESR are both frequency dependent. At higher frequencies capacitance drops and ESR increases. To insure stable operation the output capacitor should have the required values at 100kHz.

There is also a graph that shows the effects of increasing noise when this capacitor is varied: -

enter image description here

It's all there in black and white and pretty coloured lines on the graph. Additionally, this is the lowest noise and stablest regulator under £12 and you would expect to apply a capacitor on the output to ensure that high frequency output impedance is kept very low (in order to keep noise low).

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  • \$\begingroup\$ Thank you for the explanation but there's no need to be condescending. Sorry I wasn't thorough enough reading the datasheet but I didn't know the key phrases were "bypass" or "load" capacitor. When I initially skimmed the datasheet I saw the "An output capacitor with a value between 2.7μF and 100μF is also required" sentence when looking at info about the output pins and I saw the "pretty" graph but I missed the text further down, which was my fault. I still don't fully understand why "instability" leads to a simple voltage offset in this case though. \$\endgroup\$ – Magic_Matt_Man Aug 29 '17 at 18:09
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    \$\begingroup\$ Were you measuring the voltage with a meter and no, I wasn't being intentionally condescending. If you were measuring with a meter then it's likely the output was oscillating on and off and producing an average voltage of 1.75 volts. \$\endgroup\$ – Andy aka Aug 29 '17 at 18:13
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    \$\begingroup\$ @Magic_Matt_Man, Don't you know that "the best defense is a good offense?" Again, it is not about not knowing something. You expressed a lack of basic knowledge in the area of analog regulation, that every regulator (especially older designs) have limitations on load capacitor, when the range of ESR would be quoted in documentation, otherwise the regulator would OSCILLATE if ESR is too small or too high. It will start OSCILLATING, all in accord with phase margins from basic control theory. True, today we do have special LDO designs called "capless", but it was a long effort. \$\endgroup\$ – Ale..chenski Aug 30 '17 at 2:01
  • \$\begingroup\$ "Again, it is not about not knowing something. You expressed a lack of basic knowledge in the area of analog regulation..." There appears to be a contradiction here, but I don't intend to argue with you over it as I have better things to do with my life. I was ignorant of some details about analog regulation, as you have repeatedly pointed out, but I am trying to become less ignorant. Thank you for re-iterating the lesson about oscillations. \$\endgroup\$ – Magic_Matt_Man Aug 30 '17 at 11:41

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