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I'm just beginning with FPGAs and I have decided to go with verilog as the HDL. I saw a line like this: always@(posedge clk) I wanna know when is posedge used and when is negedge used. Also, what's the difference between them?

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  • \$\begingroup\$ But why always posedge? \$\endgroup\$
    – marymarlo
    Commented Aug 31, 2017 at 8:33
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    \$\begingroup\$ Have you read any Verilog tutorial? This is very basic stuff... \$\endgroup\$
    – andrsmllr
    Commented Aug 31, 2017 at 8:42

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posedge triggers the block on the positive (rising) edge of a clock signal. negedge triggers on the negative (falling) edge.

Unless you're interfacing with external logic that specifically requires negative edges, you should always use posedge. Designs that use both will generally have poor timing results, and may in some situations be impossible to synthesize at all.

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    \$\begingroup\$ Minor point - "you should always use posedge" - it might be better to say you should always use all posedge or all negedge. It doesn't really matter which you use so long as you are consistent. \$\endgroup\$ Commented Aug 30, 2017 at 20:12
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    \$\begingroup\$ @TomCarpenter That depends a bit. Some FPGAs and CPLDs may only have positive-edge FFs. In any case, other people's code (including your vendor's IP cores) will typically expect positive-edge clocks. \$\endgroup\$
    – user39382
    Commented Aug 30, 2017 at 20:22
  • \$\begingroup\$ It depends what you mean by "poor timing", on the one hand feeding between two registers of opposite clock means you have halved your available data propagation time. On the other hand it means you can tolerate a clock that arrives "early" compared to the data. This can be useful when doing relatively low speed inter-chip communications. \$\endgroup\$ Commented Mar 20, 2018 at 17:19
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    \$\begingroup\$ @PeterGreen When I said "designs that use both", I mean ones that use both edges internally as a substitute for appropriate pipelining. \$\endgroup\$
    – user39382
    Commented Mar 20, 2018 at 18:31
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In general posedge clk is used, to trigger a flop at positive edge of clock. Most of the reads and writes or state changes takes place at posedge.

negedge clk is used to similarly trigger at negative edge.This is used less frequently unless using for DDR2/3 etc. If you are writing on a posedge, reading would be useful on a negedge. That would save one full clock cycle on a read operation.

Negedge clock operation is also used in testbenches, to avoid race condition between DUT and Testbench, since both are driven at different clock edges.

A similar question you can see at What is the merit to using the negedge clock in verilog?

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