2
\$\begingroup\$

I have the following circuit which converts weak sine signal to pulses:

enter image description here

I have tried it on breadboard and it seems it works fine. In my application freq. is between 1Hz to 30Hz or max 100Hz. And the input signal Vpp will be from 200mV to 2Vpp.

Below is the collector and base currents:

enter image description here

And here below graph zoomed to show Vce which is 50mV during saturation:

enter image description here

Here are my questions:

1) I'm not sure if R2 and R3 is set correct/optimum for using this circuit for switching action even though in practice it works(I set R2 and R3 empirically). Am I oversaturating this transistor? In my second plot above Ic/Ib<10 but in its data sheet at saturation Ic/Ib should be around 10. It is a bit confusing.

Briefly I want to learn how can we calculate R2 and R3 for good saturation and what should be their rough value?

2) All the texts I have seen says Vce is around 0.2 during BJT's saturation but in my simulation(3rd plot) it is only 50mV. Why is that so?

\$\endgroup\$
  • 1
    \$\begingroup\$ Before answering I and surely the others, too, want to know what is the intended usage of the generated pulses. No optimization is possible without knowing it. Your generated pulses for example have quite slow ramps for many applications that need pulses which change their state in nanoseconds. \$\endgroup\$ – user287001 Aug 31 '17 at 23:34
  • \$\begingroup\$ Freq will be between 1Hz to 30Hz. And fast rising edges are not important since this will pull down an NPN input of another device which will take care of it. Precision is not important. \$\endgroup\$ – atmnt Aug 31 '17 at 23:41
  • \$\begingroup\$ It is saturating better than Vce(sat)@ ? mA because you are using less current than ? mA. Imagine an internal collector R, we call Rce and then you can estimate Vce(sat) \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 1 '17 at 0:07
  • 2
    \$\begingroup\$ @user134429 Is this just turning a sine wave into a square wave with perhaps hysteresis? And you really are using a \$14.2\:\textrm{V}\$ power supply? And this is driving yet another NPN circuit? I wouldn't recommend a single CE stage for this, but you say it drives another NPN circuit anyway, so it seems as though you should disclose the 2nd stage so that one might attempt to merge their functions. But up to you. Other than that, it's not clear to me what isn't clear to you. Asking "am I oversaturating" just leaves me wondering without really clarifying your quandary, for example. (To me.) \$\endgroup\$ – jonk Sep 1 '17 at 1:05
  • \$\begingroup\$ @jonk It will drive the NPN input of this: brodersencontrols.com/images/pxf-20_11.pdf 14.2V is the supply from this device(I guess this device will sharpen pulses as well). I could use another supply for the transistor as well. Regarding my circuit, the input range will be 200mVpp to 2Vpp. I checked in real this circuit works but I'm not sure R2 and R3 is set correct/optimum values. If Ic/Ib<10 does that mean something is wrong? Or is there a limit for Ib? How would you set R3 and R2 for the input range I mentioned? \$\endgroup\$ – atmnt Sep 1 '17 at 1:15
1
\$\begingroup\$

It is difficult to make a single transistor work as a limiter unless there are limits on input signal range and frequency, so you need to define these limits.

But assuming they are only for the values given, we can make it better.

When your input signal goes low Vbe turns off and the collect current shuts off and Vc is pulled up according the Rc value and ratios.

When your input goes high , collector goes low but it stays low more than half the time so the input is pulled up too much from negative feedback current.

Solution?

1) Change bias of R2 from 0V to Vcc but with a value of 10x Rc or roughly 20k

  • Why? Vce(sat) is normally rated at Ic/Ib=10

2) Change R3 from 20x Rc to 50x Rc or ~ 100K Change Rf

When Vce saturates , its voltage Vce(sat) depends on the collector current as if there was a small series R, which we can call "Rce". This value controls the Vce(sat) and Rce is reduces as device power rating increases. Then it is affected by temperature and chip design so the default spec is Vce(sat) at some rated current. Rce is similar to RdsOn in MOSFETs but not as low. You may estimate this as the rise of Vce(sat) for rise in current as long as base current is at least 5~10% of collector.

p.s.

Normally 2 devices working in differential mode give a better result then we move up to comparator designs or use a CMOS logic buffered inverter AC Coupled with high R feedback for self biasing for amazing simplicity. with large R values and much small C coupling values. like 10M and 0.1uF

\$\endgroup\$
  • \$\begingroup\$ I made a minor mistake I updated my circuit now. R3 would be directly connected to Vcc. Are you saying R2 better 20k and R3 100k? In my application freq. is between 1Hz to 30Hz or max 100Hz. And the input signal Vpp will be from 200mV to 2Vpp. \$\endgroup\$ – atmnt Sep 1 '17 at 0:29
  • \$\begingroup\$ Input is not fixed. Range is 200mV to 2Vpp. Following your logic, I set R3 to 220k and R2 to 39k; to make things better for the 200mVpp to 2Vpp input range. Do you think makes sense? \$\endgroup\$ – atmnt Sep 1 '17 at 1:04
  • \$\begingroup\$ 2V is driving too much current into Vbe , what is source impedance? WIth that range you need a better limiter than 1 or 2 transistors, BTW the F2V converter is overkill. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 1 '17 at 1:35
  • \$\begingroup\$ I noticed my max input can be 12Vpp \$\endgroup\$ – atmnt Sep 1 '17 at 1:50
  • \$\begingroup\$ this is the sensor I want to use nrgsystems.com/assets/resources/an40C-IF3-interface.pdf together with F2V converter's NPN input \$\endgroup\$ – atmnt Sep 1 '17 at 1:53

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.