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I am trying to simulate a mips-like processor using verilog. Since I am new to verilog, so I do not know if the design is correct or not. Here is the sketch of my design.

Each storage element (Register file,datamemory,AlusourceA,AluSourceB..etc) is defined in a separate module alongwith the functionality to write on that storage element. The control signals and necessary data,address are provided by hierarchical reference to other modules.

Here is an example of a module which explains my design clearly.

     /* top is the main module in this example, all
       modules are instantiated in top module. One or more registers are 
       instantiated in each module which are updated based on the contents 
       of registers in other modules using hierarchical reference*/



     module dat1dat2(input clk,output alusrca,output alusrcb);
     reg [7:0] data1,data2; /*Registers which will be cross referenced in 
                             Alu module*/
     always @(posedge clk)
     begin

     if (top.control_unit_uut.en_dat1dat2 and !alusrcb )
     /*hierarchical reference to a register in a module instantiated in top 
     module*/ 
     begin
     data1<=top.regfile_uut.regfile[top.IR_uut.IR[12:10]];
     data2<=top.IR_uut.IR[6:0];
     end

     elseif (top.control_unit_uut.en_dat1dat2 and alusrcb)


     begin
     data1<=top.regfile_uut.regfile[top.IR_uut.IR[12:10]];
     data2<=top.regfile_uut.regfile[top.IR_uut.IR[9:7]];
     end 
     else
     begin
     data1<=8'hzz;
     data2<=8'hzz;
     end
     end
     assign alusrca=data1;
     assign alusrcb=data2;
     endmodule

Is this design legal in verilog given that I don't have to synthesize it, I just need to simulate it? If the answer is no, what is the simplest design I can use which is not necessarily synthesizable?

PS: If something is still unclear about my question, I can explain it in comments or update my question.

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  • \$\begingroup\$ so, what does your verilog synthesizer / simulator say? I mean, it's nice that you expect us to foresee what could be wrong in your code, but usually, actually asking the piece of software that has to simulate it might be a better idea? What are the problems that you think about? \$\endgroup\$ – Marcus Müller Sep 2 '17 at 12:58
  • \$\begingroup\$ I have not simulated it yet, for this I would need to create other modules and write a testbench as well. I am not asking you to tell me if the code is correct or not, I am asking if registers in one instantiated module can updated based on the contents of registers in other modules or not. The code is just an elaboration of this idea. \$\endgroup\$ – Shadow Sep 2 '17 at 13:05
  • \$\begingroup\$ So, ok, "I am asking if registers in one instantiated module can be updated…", no so far, you don't. That sentence appears nowhere in your question! Please edit your question to include that :)! Also, I don't know whether you already "speak" verilog or not, but things are syntactically ... questionable, and you can synthesize things without a testbench, so that your synthesizer complains about syntax errors. \$\endgroup\$ – Marcus Müller Sep 2 '17 at 13:09
  • \$\begingroup\$ Here is the complete description: top is the main module in this example, all modules are instantiated in top module. One or more registers are instantiated in each module which are updated based on the contents of registers in other modules using hierarchical reference. Is this legal in verilog? \$\endgroup\$ – Shadow Sep 2 '17 at 13:16
  • \$\begingroup\$ I repeat: edit your question to include that! \$\endgroup\$ – Marcus Müller Sep 2 '17 at 13:19
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Yes, direct assertions are legal in Verilog. However, this is a very bad design practice to design main RTL code using direct assertions.

The direct assertions in Verilog are usually used in verification environment, in test benches, to "hot wire" some initial states and change timing parameters, mostly in order to accelerate verification process. In this way the verification environment doesn't interfere with main RTL during debug.

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  • \$\begingroup\$ What is the alternative? I thought about declaring a wire in the top module and connecting it with a module that drives it as an output and all other modules as an input that needs it. This approach doesn't work because I cannot keep the contents of a wire. Any suggestions? \$\endgroup\$ – Shadow Sep 2 '17 at 17:29
  • \$\begingroup\$ @Shadow, the alternative is to design in explicit data buses, with explicit port wires. You don't need to keep wire content, as you are not keeping content of wires like "top.regfile_uut.regfile[...]". When you write something like that, it will be still synthesized as a wire, you just have a scattered unmanagable wire spaghetti. \$\endgroup\$ – Ale..chenski Sep 2 '17 at 18:01

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