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enter image description here

This is supposed to be an amplification stage for a piezo microphone connected on J1.

The "ANLG_PWR" is at 3.0 volts. When probing the output (TP1) the DC output is at 3V.

I figured I had too much amplification and so reduced R6 from its original 1Mohm value to 200Kohm. That did improve the situation and got the output voltage down to 1.84V. When probing both inputs of U2 i get 1.48V.

Why is the DC output voltage not centered around 1.5V like I designed it to be?

I do need the original amplification (about 1:500) but need the DC output to be 1.5V.

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  • \$\begingroup\$ Why don't you try simulating this circuit in ltspice. I think that should help understanding the issue. \$\endgroup\$ – Mayank Sep 3 '17 at 5:21
  • \$\begingroup\$ Thank you but this is already a PCB with a customer waiting. I need to try and come up with a solution. \$\endgroup\$ – user1447154 Sep 3 '17 at 8:18
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    \$\begingroup\$ It's just opamp input offset voltage amplified. First one has 2mV typical, max 10mV. Second one 3mV typical. When you set R6 to 200k, i.e. gain approx 100, you have 1.84V-1.48V=360mV output. So moving this offset to input side you have around 3.6mV which fits good with a couple of typical (not worst case) op-amps. When setting gain to 500 offset is enogh to saturate your amplifier. So in short you should change amplifier not to have bandwidth down to DC which with a piezo sensor is not needed anyway. So you will only amplify AC but not DC offset. \$\endgroup\$ – carloc Sep 3 '17 at 8:47
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    \$\begingroup\$ Note also that the GBW product of this opamp is just 2 MHz. Trying to operate it with a closed-loop gain of 500 will result in a usable bandwidth that is less than 4 kHz. Is that sufficient for your application? Another way to deal with the offset issue can be found here: Avoiding electrolytic capacitors in high-pass filters with sub-Hz cut-off \$\endgroup\$ – Dave Tweed Sep 3 '17 at 11:55
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You really ought to link to the opamp datasheet in the question.

This shows the input offset voltage is typically +/-3mV. Multiply by your stage gain of -450, and you'll see the output offset voltage is about +/-1.5V, and with a single 3V supply rail, I hope you can see that will be a problem.

What you need to do is to reduce the stage gain at DC.

Incidentally you would probably be better to split the gain across both opamps, 22 in each, (well, 22 in the first, -22 in the second, if you keep the current topology) and AC couple from one to the other to eliminate accumulated offsets. Just turn U1 into a classic non-inverting amplifier (values shown give a gain of 23, reducing to 1 at DC) and reduce the gain in stage 2 to compensate.

schematic

simulate this circuit – Schematic created using CircuitLab

This will have another potential benefit : instead of one fast (unity gain) stage and one very low bandwidth stage (GBW/450 = 4kHz) both stages will have bandwidths of about 90kHz (GBW/23 or so)

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  • \$\begingroup\$ Thank you very much. I will try this. I really appreciate your help on this Brian. \$\endgroup\$ – user1447154 Sep 3 '17 at 12:30
  • \$\begingroup\$ At the end, adding just a 0.1uF cap before R4 solved the problem so i guess it was U1 DC offset voltage that was causing this. Thank you all. \$\endgroup\$ – user1447154 Sep 6 '17 at 19:29

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