I am trying to make a good layout for the Quad SPI NOR flash memory MT25QL256ABA1EW9-0SIT with the STM32 MCU. My problem is that I find the memory chip pinout quite inconvenient. I have managed to swap pins on the MCU side the way that the signals reside next to each other but it is still difficult. Following the Micron Quad spi layout guide I have managed to:

• Not split the underlying ground plane (this is a 2 layer PCB),
• Make the clock signal short and possibly with least bending,
• Use no VIAS for signals routing

However, I did not manage to:

• Keep any sensible impedance by calculating striplines (there is realy not much space and many signals)
• Keep the signal lengths similar.

Here is the layout:

After enlarging the image one can see the net names on the memory chip pads. I would like to ask you either in your opinion this design is sufficient for up to 80 Mhz clock transfer. For the comparison purposes, the pink shape in which the chip is inside of is 18 x 8 mm. The GND polygon pours are shelved for visibility. I would appreciate all help.

• Is bottom layer a full ground pour? Can you add a screenshot of the top pour as well?
– Mike
Sep 3, 2017 at 16:41
• Would it not be better to rotate it to achieve more equal signal lengths? No need to put the supply pins with the caps in between the chips - that space could be used for length matching. Sep 3, 2017 at 17:03
• That via between the two caps is a bit wierd... Did yo get away with it? Sep 5, 2017 at 18:02
• I removed it. Wanted to make a close gnd via but it was to close. Sep 5, 2017 at 18:16

For FR4, using effective epsilon of 3.25 we get the wavelength of a 80 MHz signal in the PCB at 80 by calculating

wavelength = (c/f) * (1/sqrt(epsilon)) = (300000000 m/s / 80000000 1/s) * (1/sqrt(3.25) = 2.06 meters.

Using 1/16 of wavelength as the "safe limit" below which we don't need to worry about reflections and relative signal timing, it's

safe_length = (1/16)* wavelength = 2.06 / 16 = 12.8 centimeters = 5 inches.

Your signal traces are well below that limit. Your routing is good enough.

• But there is still the crosstalk consideration. Should I make more space between the traces on purpose? Sep 3, 2017 at 17:11
• By the way, you should not consider just the fundamental of clock frequency. A more conservative approach would be to consider the fast rising/falling edges, which might be 1-3 ns... i.e. at much higher frequencies. Sep 3, 2017 at 18:06
• I think no need to overengineer it. However you look at it, the routing is well below any RF limits at 80MHz and any problems will probably not be due to routing, more possibly with pad layout or something like that. Good enough is good enough. Time to move on to next problem. :)
– PkP
Sep 3, 2017 at 19:09

From a topology standpoint you may want to consider rotating the SPI Flash chip 90 degrees left (counter clockwise) as below. This will tend to even out the natural routing lengths and allow some possibility to length match up to the MCU.

• Looks like NCS and CLK are misrouted, but the rest of the answer stands. Sep 3, 2017 at 16:58
• @IgnacioVazquez-Abrams - I just had the right side labels flipped. Corrected now. Sep 3, 2017 at 17:03
• Thanks for the answer. I tried doing it the way ypu desribed but I had the clock signal more bended. Is it more important to keep the traces lenght in similar length? The bottom side is not designeted for gnd only, its a signal layer but I intend bot to place traces underneath Sep 3, 2017 at 17:09
• Larger modern SPI flashes has thermal pad below the chip, I'd use it and avoid routing through it if possible.
– PkP
Sep 3, 2017 at 17:12
• Yes I have the thermal pad under consideration Sep 3, 2017 at 17:15