# Explanation for decoupling capacitors [duplicate]

For the longest time I have been instructed to put on 100nF decoupling capacitors between the VCC and GND pins whenever I lay out a board involving an MCU. I could not find the exact reason as to why they are needed. However, after some research online I did find a few reasons for their use. Below I explain the main reason, as I understand it, why decoupling capacitors are needed. I would like some feedback and would also like to know if this explaination is satisfactory or not.

Consider a pin of an MCU which has a single LED connected to it through a resistor. Lets say that the pin toggles from low to high, that is it turns the LED on. Now with the LED on, it will draw current which the MCU will have to provide. In return, the MCU draws more current (i.e power) from the power supply i.e. its VCC and GND pins. However, a sudden current draw by the power pins causes a voltage drop across the resistance of the power traces. Since the power supply is slow as compared to the microcontroller, it senses the drop in voltage after a little time and then changes the voltage back to its constant value again ( since it is to behave as a constant voltage source). That is where the decoupling capacitors come in. Whenever the MCU draws in a current pulse, the capacitor makes sure that the voltage across the power pins remain essentially constant till the power supply voltage stabilizes again.

That is all I have understood. Now I do not know how to calculate the exact value of the decoupling capacitor but have been told that 100nF or any value in that neighbourhood is pretty safe to use.

• Decoupling capacitors act as the C component of a RC filter on the power rail. The active electronics is the R component. – Ignacio Vazquez-Abrams Sep 4 '17 at 3:48
• decoupling is multi-purpose. Whatever you have explained is one of the purpose. There are many posts in this forum itself to talk about decoupling concept. i= c*dv/dt is the equation to calculate decoupling capacitance for a transient load demand. – user19579 Sep 4 '17 at 4:07
• Here's a related answer I typed up a while ago... – bitsmack Sep 4 '17 at 5:19
• "However, a sudden current draw by the power pins causes a voltage drop across the resistance of the power traces." - It's less about resistance and more about inductance. Resistance doesn't care about a sudden current draw, inductance does. – marcelm Sep 4 '17 at 9:51

Parasitic inductance is the major reason. A change in current causes a voltage drop across inductance proportional to the rate of change of current. This necessitates bypassing that is local to the chip. Otherwise we could just use one big capacitor for the entire power rail.

There can be and are current surges even without the LED due to the transistors charging internal and external capacitances and due to conduction through complementary pairs.

A voltage regulator also has an inductance-like behavior as you note, however usually it is swamped by a relatively large capacitor near the regulator output.

The capacitances and inductances of which I speak are parasitic- due to unwanted effects that are part of the construction- even a few cm of traces will have significant inductance and it's easy to get a few pF of capacitance. Much of the average current that a digital CMOS chip draws is just at the transitions, charging and discharging such capacitances, so it occurs in a spikey manner at the clock edges.

It is not straightforward to calculate the appropriate values because there is insufficient information, but following data sheet recommendations and rules of thumb (and good PCB layout) is typically more than sufficient. Sometimes datasheets eval boards and reference designs call out very large numbers of capacitors, perhaps 60 or 80 for a single IC with larger and smaller values paralleled for better performance. The Zynq 7000 eval board, for example, has around 150 bypass capacitors for the SOC chip.

The shoot-through current of each onchip logic gate, as that gate reverses the logic level, can be 100uA per gate[or a lot higher] for 5 volt MCUs.

This is based on Idrain = K/2 * W/L * (Vgs-Vt)^2 for source-drain spacing of 1U or more.

Let K of older Nchannel FETs be approximately 100 ua/Volt^2, and W/L of 10u/1u = 10.

We still need the (Vgs - Vt)^2 value. Assume the CMOS gate is at Vdd/2 = 5/2 = 2.5v on the input logic level; assume Vt is 0.5volt (approximately). Our result is (2.5 - 5)^2 = 2^2 = 4.

Now lets combine these values: 100uA/Volt^2 * 10:1 * 4 volt^2 = 100 * 10 * 4 = 4,000uA; this is 4mA per each gate.

Versus the 100uA I first mentioned. In truth, the PMOS device, with higher Vt and lower K, will limit the current.

Thus 1,000 gates simultaneously transitioning needs 4Amps shoot-through current. For 1 nanosecond. Thus 4 nanoCoulombs charge. With 0.1uF local charge storage (that bypass capacitor), the voltage sag is dV = I/C * T

dV = 4amp/0.1uF * 1nS = 4 * 0.01 = 40 milliVolts, upon each clocking event.

This sag in the local VDD (onchip) needs to be recharged at some rate, so cumulative sags do not reduce VDD to level where the gates cease operating and the FlipFlops cease storing bits.

• This might be a nice answer, but almost impossible to read. Doesn't EE-SE support equation/TeX markup? – not2qubit Aug 13 at 14:02