so this a homework problem that I am working on and I'm not looking for a flat out answer, just a good place to start and some help on the concept. So the question is as follows:

Suppose our objective is not to increase the total cascoded gain, but rather keep it at the single common-source stage's gain of gmRL, and extend the frequency response. Develop the theory needed to modify the Bode plot to show the new cutoff and unity gain frequency.

So what I understand so far is that the corner frequency is dependent on both internal and external capacitances of the circuit and transistors. I know that I have to account for the miller multiplier so the internal gate-drain capacitance appears larger, making my corner frequency smaller? and I also know that the corner frequency is w=1/τi where τi is the sum of the time constants, and the time constant is the resistance multiplied by the internal and external capacitances. Would adding more capacitors at the output or input to lower the total capacitance? I think that both of those solutions actually increase the time constant so it's not the direction I should go in. what about placing a small resistance between the input and output of the individual transistors?

Thanks for the help!

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1 Answer 1


When you analyze such a circuit for the first time you cannot avoid drawing the small signal equivalent circuit, so start with that.

Next step is to identify the corner frequencies. The easiest one is of course \$R_l C_l\$ or more accurately: \$R_l *(C_l + C_{ds,Mcasc})\$

Another one is at the input, the \$C_{gd,Min}\$ times the source resistance. But in order to say anything about the influence of this corner frequency we need to know the output impedance of the source driving. That's where \$R_{sig}=0\$ comes in, meaning we can ignore this pole (You know why ?)

Also note how the bode plot only shows a 1st order low-pass characteristic, it means there's only one corner frequency.

So the conclusion is that there's only one corner frequency to consider which is \$R_l *(C_l + C_{ds,Mcasc})\$

Now what happens if for example \$C_l\$ doubles in value ? The RC product becomes larger. But is RC in the nominator or denominator of the formula for a corner frequency ? So what happens to the value of that corner frequency when \$C_l\$ is doubled ? So what must be done to make the corner frequency higher (increasing the bandwidth) ?

  • \$\begingroup\$ Wow thanks! this really helped, I'm guessing Rsig is 0 so that a voltage divider doesn't form for the input signal. Also, this may sound dumb but I just want to clarify, Cds,Mcasc is the drain-source capacitance multiplied by the gain to account for the miller effect right? \$\endgroup\$ Sep 5, 2017 at 7:43
  • \$\begingroup\$ Cds,Mcasc You're seeing Miller everywhere don't you ? The Miller effect is only involved when there is a capacitor to another node and that node has the signal voltage with opposite phase. So when one side of the capacitor goes up 1 mV but the other side then immediately goes down 10 mV, then the capacitor "looks" a lot larger from the 1mV side (about 10 x larger). Is there a capacitor on the output which has its other side connected to a point where there is a signal ? \$\endgroup\$ Sep 5, 2017 at 7:55
  • \$\begingroup\$ haha sorry :p, I'm just trying to get a comprehensive understanding, no I there isn't a separate capacitor connected from the output \$\endgroup\$ Sep 5, 2017 at 8:02
  • \$\begingroup\$ Exactly, there's the Cdg of the NMOS, since the Gate is grounded, Cgd is in parallel with Cl. So no Miller effect. Cds is not mentioned and usually small so we ignore it ;-) \$\endgroup\$ Sep 5, 2017 at 8:04
  • \$\begingroup\$ I'm drawing out the small signal models and going through the corner frequencies like mentioned above. regardless of the pole of the bode plot I'm trying to go through it all so I understand better. \$\endgroup\$ Sep 5, 2017 at 8:05

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