We have an NIC (computer A) connected to Marvell 88e1116R via Ethernet cable, the Marvell chip is then connected to Xilinx FPGA, the FPGA connected to ADSL Analog front end (AFE), the AFE is connected to a phone grade twisted pair cable. At the other end of the cable there is another ADSL AFE, followed by FPGA, then Marvell PHY chip which finally connects to another NIC (computer B).

The problem is summarized in the following manner:

Data flow from NIC to PHY = ok,

Data flow from PHY to NIC = nothing!,

Data flow from PHY to FPGA = ok,

Data flow from FPGA to PHY = ok,

It's important to note that when the two NICs try to talk to each other, everything seems ok except of two issues:

1- Marvell PHY (on both sides) receives data coming from FPGA with no problem, but does not re-transmit the same data to NIC (on either computer A, or B). We tried many solutions with no luck.

2- it was noticed that both NICs try to broadcast at the same time.

If we attempt to connect the two NICs directly together (just to check our network settings) everything works fine.

We're hitting a brick wall with this issue. Your kind assistance is highly appreciated.


1- Marvell PHY crossover register set (checked).

2- Marvell reset pin (checked).

3- link status between NIC and PHY (checked).

4- loopback testing (checked).

5- PHY MAC address (not applicable in our scenario. PHY is acting as pass through device).

6- computer/NIC network settings (checked. Direct NIC to NIC link works fine, but when we add the PHY/FPGA block in between; the above problem arises).

Please help..

Best wishes, F. Sulaiman


1 Answer 1


I think you will need to simplify the problem a bit by testing.

Try implementing something like this sequence of test cases:

1/ NIC.A --- cat5 --- 88e1116 --- XIL (loopback in xilinx verilog)

If this fails, then use xilinx PCS layer loopback

What is the connection type from phy to xil, is it RGMII ?

2/ XIL.A -- ADFE.A -- tp --- ADFE.B --- XIL.B introduce a known pattern to XIL.A and check for that on XIL.B

can you elaborate a bit on the loopback testing done since there should be many many places to apply a loopback in this system

  • \$\begingroup\$ Hello Alex, thanks for your support. 1) will provide more details on loopback in a short while. And yes , FPGA-PHY link is RGMII. 2) we did this test with many known patterns, all works fine (no problem with FPGA) it is the PHY which is a suspect. \$\endgroup\$ Commented Sep 6, 2017 at 5:23
  • \$\begingroup\$ Hello again Alex, we did what you asked for: 1) loopback at PHY =all ok, 2) loopback at Xilinx =all ok, 3) loopback at pcs layer =all ok. It just happens that our earlier mentioned setup is causing both NICs to start UDP broadcasting both at once. I mean both NICs are transmitting (we use 100baseT half duplex. We cannot go full duplex due to design restrictions). The strange thing is that if we remove PHY and FPGA blocks and connect both NICs directly everything works fine without any changes. Any suggestion? \$\endgroup\$ Commented Sep 6, 2017 at 15:35

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.