We have an NIC (computer A) connected to Marvell 88e1116R via Ethernet cable, the Marvell chip is then connected to Xilinx FPGA, the FPGA connected to ADSL Analog front end (AFE), the AFE is connected to a phone grade twisted pair cable. At the other end of the cable there is another ADSL AFE, followed by FPGA, then Marvell PHY chip which finally connects to another NIC (computer B).
The problem is summarized in the following manner:
Data flow from NIC to PHY = ok,
Data flow from PHY to NIC = nothing!,
Data flow from PHY to FPGA = ok,
Data flow from FPGA to PHY = ok,
It's important to note that when the two NICs try to talk to each other, everything seems ok except of two issues:
1- Marvell PHY (on both sides) receives data coming from FPGA with no problem, but does not re-transmit the same data to NIC (on either computer A, or B). We tried many solutions with no luck.
2- it was noticed that both NICs try to broadcast at the same time.
If we attempt to connect the two NICs directly together (just to check our network settings) everything works fine.
We're hitting a brick wall with this issue. Your kind assistance is highly appreciated.
1- Marvell PHY crossover register set (checked).
2- Marvell reset pin (checked).
3- link status between NIC and PHY (checked).
4- loopback testing (checked).
5- PHY MAC address (not applicable in our scenario. PHY is acting as pass through device).
6- computer/NIC network settings (checked. Direct NIC to NIC link works fine, but when we add the PHY/FPGA block in between; the above problem arises).
Best wishes, F. Sulaiman