I am reverse engineering an embedded system which has an ARM SoC on it. I have no datasheets at all, so I am going fairly deep with the investigation.

It is packaged in a lidless flip-chip BGA. The carrier substrate that the die is mounted on provides clues to the function of pins, so I was investigating the SoC under the microscope.

I have noticed that there are a number of notches cut through the solder mask and outer layer of copper. They cut traces between the balls.

Overview of the underside of the BGA: Overview of the underside of the BGA

View of some of the notches: View of some of the notches

Oblique view showing depth: Oblique view showing depth

Traces being cut by notches: Traces being cut by notches

My initial thought was that these were used to configure the device after they had been binned. There seem to be too many though - well over 50 on a 452 pin BGA package. What are they used for?

I'm also intrigued as to how they are made. They have very square sides and no undercut given that they are only 0.25mm long, pretty much ruling out etching and laser. I can't see how a mechanical method would get such a uniform bottom.

  • 2
    \$\begingroup\$ Are you referring to the little diagonal bits of exposed metal next to some balls? It might help if you circled what you're talking about in one of the photos. :) \$\endgroup\$
    – user39382
    Sep 5 '17 at 21:51
  • 1
    \$\begingroup\$ If the notches cut some traces, it could be strap-based configuration. Or serial number. \$\endgroup\$ Sep 6 '17 at 1:15
  • \$\begingroup\$ I'm not sure those are "notches" at all. From what I can see in the photos, it looks like the copper is intact -- there's just no soldermask on it. \$\endgroup\$
    – user39382
    Sep 6 '17 at 2:46
  • \$\begingroup\$ duskwuff - I have added circles. They aren't exposed metal though, that's the underlying substrate. They are notches - as I said above, they go through the solder mask and copper, as you can see the depth and that they cut traces. \$\endgroup\$ Sep 6 '17 at 7:00

I think the links were to tie the pads together for plating. Every single pad once had a connection to the outside if I am correct. You can see traces going off the pattern on the top. After plating they CNC route out the connections.

Many of the ball pads are tied together in groups for ground and supply rails so only single traces would be required for each group.

Something similar is often done for edge connector pad plating- the connections are milled off later. I have also seen this on boards that are punched with holes to break the temporary connections.


I think you are on the right track about device configuration. They appear to be laser fusible links, some of the "slots" show bare substrate, others have copper intact, while some show oval slots in the copper.

There could be a number of reasons why they are used:

  • Increase yield of the SoC. Chip has n+1 of a component e.g. RAM banks, and n good components are selected during test.
  • Use a common BGA footprint for different devices in a family.
  • Use a common BGA footprint with die from different manufacturers.
  • Program a unique identity e.g. MAC address into the SoC.
  • Change the BGA footprint of a standard device for different markets.

Since the slots appear to open-circuit between BGA balls rather than on traces going into the substrate I would suspect the last reason. Manufacture a single device then cripple features such as external memory bus, interface ports, etc, on a low retail price device.


In my Opinion, might be to optimize impedance matching between the metallized tracks.

As we can see there is some tracks routed on a visible layer (first layer under the solder mask). The transmission mode of those lines are microstrip or coplanar grounded types.

Designers problably needed to make those lines pass here because of no more area available into other layers of the PCB stackup ( How many layers ? ).

Why impedance matching ? In order to minimize errors and signal losses in digital ( and analogical signals ) and open the "Eye Diagram" , impedances should be matched.

Therefore we can see thoses "notches" are only between connected Pads. They are forming a "Matching Network" designed for a specific frequency band (probalby a small bandwidth above GHZ).

Looking at the design from a ball Pad, it goes with a very thin line which actually behave like an inductance in high frequency, and then followed by a larger line (the rectangular notches) which behave like a capacitance in high frequency , and again a thin line until you reach the other pad.

To me, it looks like a typical Inductance - Capacitance- Inductance matching network.

Not taking into account those matching notches would result into a less performant digital transmission, with higher binary error rate.


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