JFET Burn Out in Wien Bridge Oscillator

Question

I have a simple Wien Bridge Oscillator (with JFET gain control) circuit pictured below. This circuit works as expected at lower voltages (+/-9 V), but I am running into some problems with higher voltage supplies (+/-16 V). I believe the JFET (2N3819) is burning out early in operation from some kind of transient voltage spike.

I have a supply voltage of 32 volts DC, which is then split with a virtual ground Op Amp circuit to create the +/- 16 V. From the schematic, I thought that the 25 V JFET should be fine since the greatest possible potential over it would be only 16 V. Is there an effect that might cause that transistor to exceed that voltage, or am I missing something here? Perhaps the voltage splitter allows this kind of transient?

Unfortunately, I do not have the equipment to test and record the time history of the circuit to verify the problem. I have successfully simulated the circuit in LTSpice, where the max potential developed at the gate of the JFET is within only -3 V.

If the problem is indeed with the JFET at higher voltages, what JFET might perform similarly at higher voltages? By similarly, I mean a resistance profile that allows for gain control in the Wien Bridge Oscillator.

Answer 1

From the schematic, I thought that the 25 V JFET should be fine since the greatest possible potential over it would be only 16 V.

Not actually, it might be much larger.

In the following, for sake of simplicity, all the voltages are referred to Vgnd.

When you power on the circuit, C1 is discharged, then the JFET is fully ON. The gain will be larger 3, therefore oscillations can start.

However the oscillator voltage might not stabilize without overshoots. If by chance, the oscillator reaches an amplitude of of +/- 14V (we must take the Vsat of the op amp). Then, C1 quickly charges to -13.6V, quickly opening the JFET.

In the next semiperiod, of course C1 will hold that -13.6V and the JFET will be still open. The output of the 2134 arrives unattenuated to the JFET, as the JFET is fully OFF. Since the JFET is still open, it see a gate to drain voltage of -27.6V, which is larger than the absolute maximum ratings.

Finally, U4 does not instantaneously generate the virtual ground. This might directly polarize the gate-source junction.

Possible solution?

Since the critical gain is 3, then you don't have to let the OA having a DC gain of 1, to dampen oscillations amplitude larger that your setpoint. In other words, there's no need for an infinite resistance of the JFET. If you put a 10kOhm resistor in parallel to the JFET, the maximum gain won't be affected. The minimum gain will be 1.7, which is not enough to start oscillations (i.e. it will be low enough to reduce excessive oscillation amplitudes). With such a resistor, in the conditions I described above, the most negative gate-drain voltage would be -13.6 - 5.7V = 19.3V, which is in the limit. I don't know if this will have a large impact on the oscillation amplitude stability though.