# LTSpice: 74HCT Library - Setting 74HCT74 D F/F Initial State

I am using the 74HCT library from the Yahoo user group. I currently have two 74HCT74 D flip-flops in my circuit but I do not know how to set their initial state (Q = LOW for both). Is this done in a spice directive, or is it done elsewhere?

I would include the contents of 74HCT.lib but I exceed the character limit. The files can be accessed from the link above, though, provided you are a member of the group.

• Have you tried naming the net and using .ic V(nameq1)=0 V(nameq2)=0? Not sure if that will produce the wanted effect though, maybe you need another node to set to 0. – Arsenal Sep 6 '17 at 12:44
• @Bimpelrekkie That seems like more of a hack than a solution to me. – DerStrom8 Sep 6 '17 at 13:07
• @Arsenal that did not seem to work. I would have expected there to be a setting somewhere to declare the ic of a f/f – DerStrom8 Sep 6 '17 at 13:07
• It's not a hack, it's wrong. The reset inputs to a 74xx74 is active low, so the proper approach is to start at ground and then go to Vdd. – WhatRoughBeast Sep 6 '17 at 13:32
• @WhatRoughBeast You're right, I put in a transistor to pull it low on startup and release it after a period of time – DerStrom8 Sep 6 '17 at 13:44

## 1 Answer

I don't use LTSpice, but I assume the parts conform to reality. The 74xx74 flip flops have both asychronous reset and preset. Since the parts themselves do not have any other reset functionality, the simulator cannot provide such a function - it's up to you. The simulator is simulating part behavior, not logic behavior, so a built-in reset would not faithfully simulate the circuit.

The circuit you want is called a POR (Power On Reset), and is usually provided by something like

simulate this circuit – Schematic created using CircuitLab

where the inverter is a Schmitt trigger such as the 74HC14. This works in a simulator since all simulators default to zero volts across a cap at startup. For driving 74xx logic, of course, a second inverter is required since TTL almost always uses negative logic for reset and preset functions (with a few exceptions such as the 7490 and 74173).

In simulation, this can be replaced with a pulse generator which produces a (usually) low pulse for a few 10s of nanoseconds after simulation begins.

And yes, you need to be careful about the reset function interacting with logic behavior while it's active, but you need to do this anyways in a real circuit. Fortunately, asynchronous resets (and presets) in most logic chips override all other inputs, so there is usually not much need to worry.

• I am well aware of POR circuitry, I guess I just thought there would be a way to include it implicitly in LTSpice. So far it doesn't look like there is, though, so this will do. Thanks! – DerStrom8 Sep 6 '17 at 14:00