The sophistication of your clock gating depends on how much the downstream logic is going to respond to a bad clock pulse.
For example: If the downstream logic is always reset after the clocks switch then you can get away with almost anything for your clock gating logic.
However, if you are expecting the downstream logic to continue functioning properly when the clocks are switched (without a reset) then you gating logic must be designed so that you never have clock pulses that are too short and violate your timing constraints.
The danger with short clock pulses that violate your timing constraints is that it could put a state machine into an invalid state that it can't recover from. This is really easy to do, so don't take it for granted that it won't happen to you.
Designing good clock gating/switching logic that doesn't produce short clock pulses is difficult and usually requires intimate knowledge of your ASIC process. Rather than invent your own, I suggest that you talk with your ASIC house or whoever you got your ASIC libraries from. Odds are very high that they already have the circuit you need.
The OP indicated that the clock gates in the schematics are from the ASIC library. If those gates are designed to not glitch (I.E., they never produce a pulse that is too short), then the only trick is to allow enough time between disabling one clock and enabling the next. In this way you can cleanly switch between clocks and not have clock glitches.
Designing the logic to do this (keep enough time between disable/enable) is still difficult, but not super difficult. On a scale of 1-10, this would be a 6. Designing a glitchless clock gate, on the other hand, would be a 10 or even 12!