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I am working on an ASIC design and need to use different clock sources for a digital block in different operating modes.

Can I safely use clock gating in combination with an OR gate to generate the clock as in the following diagram?

Schematic

If that is ok, what constraints do the clk_enable signals need (i.e. glitch-free, non-overlapping, timing with relation to the respective clk, ...)?

Note that the clock gates are using a D-latch which is transparent when the respective clk is LOW.

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The sophistication of your clock gating depends on how much the downstream logic is going to respond to a bad clock pulse.

For example: If the downstream logic is always reset after the clocks switch then you can get away with almost anything for your clock gating logic.

However, if you are expecting the downstream logic to continue functioning properly when the clocks are switched (without a reset) then you gating logic must be designed so that you never have clock pulses that are too short and violate your timing constraints.

The danger with short clock pulses that violate your timing constraints is that it could put a state machine into an invalid state that it can't recover from. This is really easy to do, so don't take it for granted that it won't happen to you.

Designing good clock gating/switching logic that doesn't produce short clock pulses is difficult and usually requires intimate knowledge of your ASIC process. Rather than invent your own, I suggest that you talk with your ASIC house or whoever you got your ASIC libraries from. Odds are very high that they already have the circuit you need.

Update:

The OP indicated that the clock gates in the schematics are from the ASIC library. If those gates are designed to not glitch (I.E., they never produce a pulse that is too short), then the only trick is to allow enough time between disabling one clock and enabling the next. In this way you can cleanly switch between clocks and not have clock glitches.

Designing the logic to do this (keep enough time between disable/enable) is still difficult, but not super difficult. On a scale of 1-10, this would be a 6. Designing a glitchless clock gate, on the other hand, would be a 10 or even 12!

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  • \$\begingroup\$ The clock gate as shown in the schematic is exactly that: a cell I got from the ASIC library. That cell only gates one clock though, what I need is something to switch a couple of clocks. My question therefore is if that OR gate solution is OK and which restrictions it imposes on the enable signals. \$\endgroup\$ – AllInOneBoat May 28 '12 at 2:19
  • \$\begingroup\$ I heard of the problem having many different names: metastability, clocking domains boundaries, glitches, plesiosynchronisity. I think it was never resolved. I think that the only solution with guaranteed integrity for crossing clocking domains is voting. Say serial communication chips or ethernet. \$\endgroup\$ – user924 May 28 '12 at 2:23
  • \$\begingroup\$ @AllInOneBoat If the clock gates are guaranteed to not glitch the output then you could do exactly what you drew IF you allow enough time between turning off one clock before enabling the next one. \$\endgroup\$ – user3624 May 28 '12 at 2:32
  • \$\begingroup\$ @RocketSurgeon: If the switching is done correctly, there should be no metastability concerns since the clocks are controlled synchronously. Using the clock gating cell shown in the schematic, there are no glitches on gated_clk. The question remains, if combining several of them using an OR gate would a) work glitch-free and b) what constraints are required for the enable signals. \$\endgroup\$ – AllInOneBoat May 28 '12 at 2:33
  • \$\begingroup\$ Agree to 99%. The remaining 0.99% of problem is race conditions (that is one more else name to the "same" problem) \$\endgroup\$ – user924 May 28 '12 at 2:35
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EEtimes has an article talking about glitch free clock switching circuit. Based on this article, Young Rhoney also has a good blog, 2x1 and Nx1 clock switching.

As explained, the key idea to do glitch free clock switching is to turn off one clock before turning on the other one. The blog also gives circuit for Nx1 clock switching.

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In addition to David's comments: there are risks past short clock pulses. Unless you can issue an iron-clad guarantee as to the validity of the clock enable lines, you might want to consider controlling the clock enables by the output of a decoder, to avoid (for example) superimposing multiple clock signals through the OR. If you can guarantee that they have the same frequency and phase, it isn't a problem, but then there probably wouldn't be a point to having multiple clocks in the first place.

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  • \$\begingroup\$ Driving the clock enables from a decoder might make them (more) glitchy... wouldn't that be a problem in itself? \$\endgroup\$ – AllInOneBoat May 28 '12 at 5:26

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