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I have a strange problem with the MOSFET Push-Pull configuration of an output stage of a simple buck converter.

On the falling edge of the Low-Side MOSFET I get an effect like ringing, but it is actually following the rising edge of the other MOSFET. What can it be? Can it be caused by stray inductance and the current of the High-Side MOSFET induces some into the gate of the Low-Side MOSFET?

I will include three pictures. One with the circuit, one with the PCB (Some explanations under the picture) and the last one with the problem.

Schematic: Schematic

PCB: PCB traces The green trace is carrying the Low-Side MOSFET signal and it goes right under the pin where the High-Side MOSFET signal is outputed from the IR2011 (MOSFET driver). Could this be the problem?

Oscillogram of the MOSFET driving signals (blue - Low-Side, yellow - High-Side):

enter image description here

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  • \$\begingroup\$ Your question has insufficient traces on Gate Signals, Ground Noise, and Schematic missing parts, e.g. R10 D7 etc. Hence gate charge current ripple , crosstalk, and ground shift are normal aspects to avoid in layout with part selection. Trace timing, Deadtime, load impedance, just for starters... Can you analyze this? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 6 '17 at 18:05
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When the high side FET starts to turn on, the switch node rises rapidly. This dV/dt causes a current in the gate-drain capacitance of the low side FET. This current tends to pull up on the low side FET gate, and can ring with the stray inductance.

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  • \$\begingroup\$ Can I do something to avoid this? I am guessing this causes additional switching losses in my circuit. \$\endgroup\$ – Cezar Chirila Sep 6 '17 at 17:32
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    \$\begingroup\$ Lowering the gate drive impedance is one thing. Maybe reducing the gate drive resistor on the low side. Some find adding a little additional gate to source capacitance helps, but that increases gate driver switching loss, so it's a tradeoff. \$\endgroup\$ – John D Sep 6 '17 at 17:39
  • \$\begingroup\$ Also finding a different MOSFET with a lower Cgd/Cgs ratio is an option. \$\endgroup\$ – John D Sep 6 '17 at 17:47
  • \$\begingroup\$ Ballast capacitence on gate-soirce and R-C snubber comes to mind too. \$\endgroup\$ – winny Sep 6 '17 at 18:33

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