I came up with voltage levels of TTL logic.

I know that logic high is 2-5V for input and 2.5-5V for output.

But why there is an additional 0.5V rise in the logic HIGH of output. Is there any specific reason?

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    \$\begingroup\$ That is to make sure a TTL output may drive a TTL input in any case, even if there is an additional voltage drop caused by the wiring. \$\endgroup\$
    – Janka
    Sep 6, 2017 at 19:54
  • \$\begingroup\$ I personally cannot say anything about that difference (I really wonder where that info comes from, btw); but according to my knowledge, voltage levels between 0 and 33% of supply (i.e. 5V) are logic low, and voltage levels between 67% and 100% of supply are logic high. This applies for both input and output. \$\endgroup\$ Sep 6, 2017 at 19:55
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    \$\begingroup\$ @RohatKılıç: The 1/3, 2/3 limits are for the CMOS families (74HC, 74AC, etc). Original bipolar TTL (74nn, 74LSnn, 74ALS) has lower high-level thresholds. \$\endgroup\$ Sep 6, 2017 at 19:59
  • \$\begingroup\$ yep rohat, cmos has both input and output with same logic levels. but ttl is exceptional that it has different logic for input and output \$\endgroup\$ Sep 6, 2017 at 20:04

1 Answer 1


That is a defined Margin for transient ringing, and standards are based on load current for recommended layouts with decoupling on each IC.

The actual TTL threshold is two diode drops or 1.5V input and output depends on logic family drive current for a fanout of 10. Fast forward 40 yrs to 74HCTxx and we have the same in/out threshold as TTL was but with rail to rail output.

If you can read schematics, it is clear how 3 TTL familiies 74, 74LS and 74S each with different speeds and output R current limits are designed differently to achieve the same voltage specs.

Remember that unless it has hysteresis like Schmitt Trigger inputs each logic device is a linear gain and behaviour during transition within these limits which are subject pn junction thermal offsets and potential ringing on transition. These input levels are meant to be also what is TTL compatible, even if design is using CMOS with T in the prefix, like 74HCTxxx

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Ringing is inevitable when prop. delay in trace length exceeds rise time due to impedance mismatch.


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