# Capacitor DC Bias Characteristic question

If ceramic capacitors lose their capacitance values quickly with increasing voltage (for example most capacitors I looked at from Murata and TDK have a curve like this)

how do IC manufacturers specify what capacitances to use? For example if they say to use a 10uF capacitor - does that mean I should a find a capacitor that will give me 10uF at the voltage I'm operating at ? Or do they say this knowing that the 10uF cap I use will be lower to some extent?

Usually they mean they want 10uF in reality, up to you to pick a cap that will deliver, sometimes this really matters, TI rail splitters, looking at you....

I would note that the voltage derating thing is MUCH worse once you get down below about 0603 package size or so, and also when you start using the funkier dielectrics.

This voltage characteristic is common to all high K, such as Y5V,X5R,X7R,X2S etc ( high density ) ceramics each with special additives to regulate the temperature coefficients vs cost factors in parts that are <0.01\$ in volume.

Therefore designers ought to be well aware of the choices for precision vs cost in designing filters and get much more than you need with many types 10nF, 0.1uF, 10uF, 1000uF depending on need for ESR and ripple current rather than just C value.

In each family of X5R caps, OEM can choose different control bin codes for tolerances on each effect in different ranges. This requires good EE experience on ceramic characteristics, supplier consistency (quality) and design stress margin.

## e.g.

• 50% of the rated voltage, B1: Within +10/-30% R1: Within +15/-40%
• zero bias: temp range.
• B1,B3 : Within +/-10% (-25°C to +85°C)
• R1,R7 : Within +/-15% R6 :(-55°C to +125°C)