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I'm currently doing the practice problems for CMOS VLSI Design 4th Edition. Question 1.6 says to use a combination of CMOS gates to generate the following functions (solution attached below function given from book answers):

$$Y=A (Buffer)$$

enter image description here

$$Y= {\overline{A}B+\overline{B}A}$$ enter image description here

My question is regarding the outputs.

For the first function (buffer) what is the point of using two inverters? Why can't I just draw a buffer? And why does the second inverter need to be active low?

For the second function, same thing, why does the output need to have an active low inverter? why can it just contain an OR gate at the output instead of a NOR and an inverter?

My best guess is that it's used to produce 'strong' outputs. But that explanation doesn't fully help with my understanding.

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    \$\begingroup\$ While non-inverting buffers are always 2 stage inverters , while inverters, you have an option U (unbuffered =1 stage) or default 3 stages. Each stage has a linear gain and a propagation delay so there are situations where this matters. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 8 '17 at 15:43
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If the only criteria is that a combination of gates be used then there could be an infinite number of 'correct' answers. However,

what is the point of using two inverters? Why can't I just draw a buffer?

  1. A single buffer is only one gate, not a 'combination'.

  2. In practice a CMOS buffer is made from two inverters, so the answer given is the simplest combination of 'elementary' gates.

And why does the second inverter need to be active low?

The negation would be equally valid on the output, but having it on the input shows that the signal is 'active low' at this point.

For the second function, same thing, why does the output need to have an active low inverter? why can it just contain an OR gate at the output instead of a NOR and an inverter?

Same thing. A CMOS OR gate is already a combination of a NOR gate and an inverter.

enter image description here

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For the first question, you can't just draw a buffer because you are being asked how a buffer is implemented. Fundamentally, a buffer is two inverters back-to-back, as shown here. cmos buffer

Why does your author draw the second inverter with the bubble on the input? It's a matter of preference. The author likely thinks that it helps prevent feeling that the output is inverted with respect to the input of the circuit. In other words, he wants to make it clear that the output of the second stage follows the input of the first stage and is not ultimately inverted.

See: wiki buffer gate

The second question is similar. You can't simple use an or gate because it is not a fundamental gate - it is constructed from a nor gate with an inverter follower. Like so: cmos or

wiki or gate

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    \$\begingroup\$ Not "two inverters back-to-back" but front-to-back \$\endgroup\$ – Curd Sep 8 '17 at 7:53
  • \$\begingroup\$ @Curd fair point \$\endgroup\$ – Blair Fonville Sep 8 '17 at 14:06
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\$ Y= {\overline{A}B+\overline{B}A} \$ is \$ Y=xor(A,B) \$ or simply \$ Y=(A \neq B) \$, being a usual implementation (see here for this implementation and alternatives):

enter image description here

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The basic gates (AND, OR, NAND, NOR) have their deMorgan's equivalent.

The basic gates are positive-input gates, which makes the deMorgan's symbols negative-input gates. Two ways to look at the same device.

NAND gate

NAND gate \$ \overline {A\cdot B}\$ with deMorgan's \$ X = \overline A + \overline B\$ becomes a Negative-input OR gate.

By using positive-input or negative-input gates, an author can identify the active state, which helps trouble-shooting. Without having to check anything else, a trouble-shooter could identify a possible problem, just by looking at the symbol used.

It is not particularity useful in your case, but it was when you had levels of gates in discrete design. For chip selects, it clearly identified the active state (low or high).

In the following example, the OR gate is shown as a Negative-NAND, because Chip Select and Output Enable both have to be low to activate output buffers. If the device was supposed to be active and no 0 was seen on input, problem found.

Active low logic

The use of Negative-Logic makes a SR NAND flip-flop so much easier to understand. Any input 0, means corresponding output is 1. It even looks similar to a SR NOR flip-flop.

Negative-Input SR flip-flop

It was also more prevalent with TTL circuits, since TTL could sink more current (low) than source, which effected the fanout or number of devices a TTL output could drive.

You do not see it very often these days, but I do smile when I do.

Negative-NOT

A 1 on A, will produce a 0. A 0 on the Negative-NOT, will produce a 1, and vice-versa.

$$Y = \overline{\overline{A}} = A $$

This is not overly meaningful, but Y = A. The inversions cancel each other out, so are irrelevant. The author is highlighting this.

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Why not do the functions using NAND gates? There's a neat XOR gate circuit:

schematic

simulate this circuit – Schematic created using CircuitLab

This gets rid of the confusion about active-low inputs. I also like that it is a single-package implementation.

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