Recently in class I have encountered the following calculation of the propagation delay of the following digital circuit: enter image description here enter image description here

Could anyone please explain to me the addition of the rising time of X2 and C? I fail to understand why this addition is regarded as the "real" propagation delay.

  • \$\begingroup\$ Did the question mention what family of devices are being used, CMOS, TTL, ECL, etc..? I am trying to make sense of where the divide by 2 comes from. \$\endgroup\$ – Entrepreneur Sep 9 '17 at 4:12
  • \$\begingroup\$ I believe cmos... \$\endgroup\$ – Meir Franco Sep 9 '17 at 8:17
  • \$\begingroup\$ I am surmising that by tr(C) they actually mean tr(Y0). The threshold voltage for CMOS logic levels is around 1/2 the supply voltage, so maybe they are emphasizing that the rise time of the input signal to reach the 0-->1 (0.5 supply voltage) threshold is non-zero and likewise with the output signal effect on the target destination. I am unsure. These delays are generally small compared to other delays. \$\endgroup\$ – Entrepreneur Sep 10 '17 at 23:41

I think it's because of the way propagation delay (say \$t_{pLH}\$) is defined. See the figure:

enter image description here

Conventional, it is measured between the mid-points of the transition.

Now if you define real propagation delay (\$t_{p,real}\$) as the time duration between the point at which input started rising and the point at which the the output settles to final value, then one can write:

real propagation delay = time required for input to rise to 50% + propagation delay + time required for output to reach final value from 50% point. $$t_{p,real} = t_{pLH}+t_{in,0\to 50\%}+t_{out,50\to 100\%}$$

So that's why half of rise times are added with the conventional propagation delay to calculate the real propagation delay.

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