# Maximum frequency of the synchronous counter

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is 10 ns. Also assume that the setup time for the JK inputs of the flip flops is negligible.

My analysis :-As it is synchronous counter so,by 10ns all the flip flop will produce output.But now the output should reach the AND gate also ,so that when next clock comes then inputs to FF are ready.

The first AND gate will produce output by 10 ns,and then this input goes to second AND gate,which takes 10 ns. So overall the time period of the clock is 30ns. And frequency is 1/30 GHZ

But my book says that clock time period is 20 ns. Can anyone clear the confusion here ,how 20ns is possible?

## 5 Answers

The book is wrong. The minimum clock period is 30 ns.

• First FF clock-to-Q: 10 ns
• First AND gate in-to-out: 10 ns
• Second AND gate in-to-out: 10 ns
• Setup time to third FF: 0 ns

Total: 30 ns

This is the time required from when the output of the first FF goes high (while the other two FFs are already high) to insure that the third FF goes low on the next clock edge.

EDIT: There's a surprising amount of confusion about this, so here are some diagrams that I hope will make it clear.

The first shows the counter counting from the all-zero state, with each horizontal space representing 5 ns. The FF and gate delays are shown as exactly 10 ns. Note that the J2K2 input to the third FF just barely makes it in time for both the 01x and 11x states.

         __    __    __   |__    __    __    __   |__    __
clock __/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__
_____    :  _____       _____    :  _____       ___
Q0    ____/     \_____/   | \_____/     \_____/   | \_____/
_____  :    _____       _____  :    _____       _
J1K1  ______/     \_____/ |   \_____/     \_____/ |   \_____/
___________             ___________
Q1    __________/   :     | \___________/   :     | \_________
_:     |___             _:     |___
J2K2  ____________/ \_____/   \___________/ \_____/   \_______
|  _______________________
Q2    ______________________/                     | \_________
|                       |
10ns  ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^


The dotted vertical line shows the case where Q2 is not supposed to toggle, and the solid vertical line shows where it is.

A conservative design (in the absence of any minimum propagation delay specifications) would assume that the outputs of the FFs and gates become invalid as soon as any input changes. Here's an expanded view that takes this into account:

            _____       _____       _____      |_____
clock _____/     \_____/     \_____/     \_____/     \_____
_______________        :_______________
Q0    _____/XXX/       \XXX\_______/XXX/       \XXX\_______
___________________    :___________________
J1K1  _____/XXXXXXX/   \XXXXXXX\___/XXXXXXX/   \XXXXXXX\___
___________________________
Q1    _________________/XXX/       :           \XXX\_______
__________ : ___________________
J2K2  _________________/XXXXXXXXXX\_/XXXXXXXXX/ \XXXXXXX\__
|___________
Q2    _________________________________________/XXX/
|
10ns   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^   ^


Here, I've shaved a little bit off the delay of J2K2 to illustrate how it just barely becomes valid in time for the two key clock edges. To summarize, Q0 becomes valid 10 ns after the clock edge, J1K1 becomes valid 10 ns after Q0 becomes valid, and J2K2 becomes valid 10 ns after J1K1 becomes valid, which is just in time for the next clock edge.

Also, as Brian Drummond pointed out, I'm completely ignoring the carry output of the circuit (the third AND gate). The question is only about the maximum clock frequency of the counter itself. If that output needs to be valid, then the clock period will have to be even longer.

• :- In case of synchronous counters we need to make sure that the input of all the Flip flops are ready before the next clock pulse comes or we have to make sure that the current flip flop output reaches to the next flip flop input before the next clock pulse comes? – rahul sharma Sep 10 '17 at 20:31
• The bottom line is, the J and K inputs must be stable just before (setup time) and just after (hold time) each clock edge in order to unambiguously determine what that FF's next state will be. – Dave Tweed Sep 10 '17 at 21:08
• @DaveTweed J1K1 will be 1 first, after 20ns right ? 10ns(FF0) + 10ns(AND gate 1) ? How is it going high after 10ns ? – Zephyr Oct 9 '17 at 18:48
• @Zephyr: I don't understand your question. We're all saying that J1K1 requires 20 ns to become valid after each clock edge. Where are you seeing 10? – Dave Tweed Oct 9 '17 at 19:24
• @anir: I addressed that in the very last paragraph of my answer. – Dave Tweed Sep 5 at 21:59

Unless the book defines "operate" you can't answer this question.

As Dave Tweed says, these three FFs can toggle at 30ns period.

However, note that the Carry output isn't valid yet.

I can't tell from the word "operate" whether or not the Carry output is intended to be valid before the next clock edge. Only the detailed specification for this counter can tell you that - so you might want to be conservative and call it 40ns to cover the Carry chain..

• Yes, I ignored the carry output, since there were no requirements either specified or implied for it. – Dave Tweed Sep 9 '17 at 12:11

The book is right.

The logic for a JK Flip flop is as follows:

There is no SET/REST used so you have to consider only Latch and Toggle for any flip-flop.

So consider Q0, Q1 and Q2 are all = 0 as an initial state

1. First Clock. Q0 + 10 ns --> 1, Q1 = 0, Q2 = 0
2. First AND gate + 10 ns --> 1, Second and third AND gate outputs = 0 (notice that no delay is incurred)
3. Second Clock. Q0 + 10 ns --> 0, Q1 + 10 ns --> 1, Q2 = 0
4. First AND gate + 10 ns --> 0, Second AND gate + 10 ns --> 1, third AND gate = 0
5. Third Clock. Q0 + 10 ns --> 1, Q1 + 10 ns --> 0, Q2 + 10 ns --> 1
6. First AND gate + 10 ns --> 1, Q1

Or timing diagram:

I set the delays as about 9 ns so allowed for setup time and the clock at 20% to make it easier to see. The clock can run at 50 MHz with only 2 delays significant.

• Note that your timing diagram is showing completely incorrect behavior for a synchronous counter. Furthermore, the critical path only comes into play between the 7th and 8th clocks, on the transition from all-ones to all-zeros. If the clock period is not >30 ns, the setup time to the third FF is not met. – Dave Tweed Sep 9 '17 at 11:00
• If you think it's wrong, then you draw it....I believe you will find you are wrong. TimingTool.com You're dealing with it as a counter, it is not. – Jack Creasey Sep 9 '17 at 14:59
• See the edit to my answer. And I was wrong in my comment above -- the critical path is involved whenever Q1 is high, because that's when the transitions on Q0 need to propagate all the way through to J2K2. – Dave Tweed Sep 9 '17 at 16:47

While I disagree with the book, and agree with the OP and Dave's answer of 30nS, I think it's worth being a bit more wordy about what's happening.

The first flip flop always toggles, ones further to the right get enabled progressively from the left.

Although the flip-flop outputs change synchronously, the purely combinatorial AND tree gives 10nS per stage delay as the enable propagates right.

If a 4th flip-flop was added, the delay would increase to 40nS.

The problem with this circuit is that the fastest toggling flip-flop is a (potentially) long AND tree away from the enable input of the rightmost flip-flop. As you increase the number of stages, the counter slows down. To see a configuration that propagates the enable in the opposite direction, so results in no slow as you add an arbitrary number of stages, see patent EP0469738A2, figures 5 and 6.

• Did you cite the wrong patent? That one shows only asynchronous counters, and the critical path is actually much longer than it is for the synchronous counter. – Dave Tweed Sep 9 '17 at 11:11
• If you read the specification, you'll see that the control path is local rather than global. Yes, the stages are asynchronous, but the point is that the propagation goes the opposite way, so the slower stages build from the left, such that the fastest edge only passes through one gate, instead of the whole chain as in the OP's question. The OP's circuit slows down as you add more stages because the fastest signal has to pass through the whole chain of AND ates. – Neil_UK Sep 9 '17 at 13:05
• I understand exactly what the patent is saying. But I still don't see how it applies to the synchronous counter here. The synchronous counter requires all of the intermediate results of the carry chain, so you can't just "reverse the gates". – Dave Tweed Sep 9 '17 at 13:50
• What I'm saying is that there exist counters where the propagation is the other way round, which result in no speed degradation as stages are added. I'm not saying that with this specific diagram, you can simply 'reverse the gates'. As I said in my answer, 'to see a configuration ...' – Neil_UK Sep 9 '17 at 14:34
• "... no slow[down] as you add an arbitrary number of stages" is an overstatement anyway. Eventually you get to a point where the long delay through N FFs and N gates begins to affect the behavior on subsequent clock edges. – Dave Tweed Sep 9 '17 at 15:08

The outputs are in sync and the max number of input delays is 2 stages.

Pullup=1 is not a dynamic input.

The gating item is actually the Terminal Count output , let me call it as it is often labelled as TC=1, when each Register Q=1. In order to cascade this design further or to make the output of last AND gate useful or at least valid for some finite time, one must add up all the prop delays of the TC relative to the clock.

You now see there are 4x 10ns prop delays = 1 FF + 3 AND gate so the maximum clock rate is 25 MHz.

The problem with this TC design is the ripple effect is sub-optimal. The preferred method is to use multiple input AND gate so there is only 1 unit delay ( which is actually NAND + INV)

• Yeah, it's 2 stages. However, the first stage is 20 nsec (FF propagation delay to output plus AND delay), while the second stage is 10 nsec (AND delay). So total required is 30. – WhatRoughBeast Sep 9 '17 at 13:36
• see update just added. To prove any method, assume all time delays are zero except one compment type, then do the same for the next and then add the sum. Include setup time and analyze for transition for asymmetry. To find the critical path, choose the max value. In this case , the last gate out. – Tony Stewart Sunnyskyguy EE75 Sep 9 '17 at 14:15