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I have placed two additional vias on the thermal pad of the IC. Though the datasheet does not specify thermal holes, but I just did them to connect the pad with the internal ground plane (2nd layer). I am not able to figure out, why altium claims that there is an error and the vias are not connected. Why shall I connect the vias with extra track? Are not they connected through the ground plane? Please help. This happens many times with me.

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  • \$\begingroup\$ Check the via's net \$\endgroup\$ – Axis Sep 10 '17 at 5:03
  • \$\begingroup\$ It's set to GND net \$\endgroup\$ – Rakesh Mehta Sep 10 '17 at 5:22
  • \$\begingroup\$ Are the vias set as "Plated"? \$\endgroup\$ – Tom L. Sep 10 '17 at 7:22
  • \$\begingroup\$ Yes @TomL. They are marked as plated.. I have added another screenshot \$\endgroup\$ – Rakesh Mehta Sep 10 '17 at 7:53
  • \$\begingroup\$ Not sure, but seems like the vias are not properly connected with Ground Plane (Layer 2) because of the thermal relief cutouts. I am a newbie, so might be wrong :) \$\endgroup\$ – Rakesh Mehta Sep 10 '17 at 8:03
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That was definitely the Pads were not connecting to the Ground Plane well due to the Thermal Cutouts. I had to disable the cutout by creating a new rule for such Pads and it seems the error is gone now :)

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