I'm looking in the datasheet and layout guide of the DP838481 but I can't seem to find where it talks about length matching for the RX and TX differential pairs. It only mentions length matching for the MDI signals.

In this guide for 82579 Gigabit PHY chip (much faster than what my chip is operating at ~10/100 Mbps) it says to keep each differential segment within 5 mils. But in the MDI interface section it also says not to use serpentine routing!

"Do not use serpentine routing (zig zag of shorter trace) to match the trace lengths. Serpentine routing to the RJ- 45 connector which connects to long out-of-system unshielded cables can contribute to radiated EMI and can decrease immunity to ESD" Page 18 of 82579 Datasheet

How close should my differential pairs match ? And should we really not use serpentine routing for these signals ?

Thanks in advance!


2 Answers 2


Modern serial full-duplex interfaces have built-in synchronization in each direction. The protocol handshakes are asynchronous, and ACKs/NAKs can come back with delays of milliseconds. Thus the Rx and Tx channels are largely independent on the bit-interval scale. As result there is no restrictions on delays between Rx and Tx lanes, and there is no need in trace length matching between differential pairs. However the trace length within each differential pair should be matched as best as you can.

The Intel layout checklist says, on page 18:

The pair to pair length matching is not as critical as the in-pair length matching but it should be within 2 inches.

These 2 inches give plenty or room for a layout designer to avoid the unnecessary serpentine. I know this for sure in USB SuperSpeed layout, but it looks like the same holds for the Ethernet PHYs.

  • \$\begingroup\$ But the 2 inches is for 2 pairs, for interpair matching it says "The in-pair trace length matching for each differential pair must be within 10 mils on a segment by segment basis." How can you do this without serpentine routing? \$\endgroup\$
    – VanGo
    Commented Sep 10, 2017 at 19:55
  • \$\begingroup\$ With usual trace width of 5-6 mils, 10 mils is not much a room for serpentine. The differential traces usually come from adjacent pins and go to adjacent pins, so it would be really difficult to have + and - traces with length difference of 10 mils (unless something really stupid is done). \$\endgroup\$ Commented Sep 10, 2017 at 20:08
  • \$\begingroup\$ But if you look at these RJ45 connectors the RX+ and RX- are seperated by 2.54mm - way more than 10 mils, what to do in that case to match length? mouser.com/ds/2/336/-370307.pdf \$\endgroup\$
    – VanGo
    Commented Sep 10, 2017 at 20:29
  • \$\begingroup\$ @VanGo, you approach the pin pair in symmetrical way. \$\endgroup\$ Commented Sep 10, 2017 at 20:33
  • \$\begingroup\$ @VanGo, please keep in mind that for 100Mbps signal (62.5MHz main frequency) all this nitpicking is not worth to worry about. 0.1" trace difference is just 15ps in timing, which is just 0.2% of signal eye. \$\endgroup\$ Commented Sep 10, 2017 at 20:54

The issue is EMI from skew and impedance mismatches on board from being radiated on long UTP cables. Even though the transformers do a good job in raising CM impedance and summing the differential impedance, they cannot cancel diiferences in overshoot or skew.

Your spec indicates ...Trace length matching, to within 2.0 inches on the MII or RMII bus is also recommended....

wavelength = 2x10^11mm/s /50MHz = 5000 mm so 2" or 51mm is equivalent to 1% skew or -20dB power reduction of the 1Vpp differential signal.

  • \$\begingroup\$ Right - so are the RX and TX differential pair also considered RMII signals ? I thought the RMII signals were only the ones going between the PHY and the MCU ? \$\endgroup\$
    – VanGo
    Commented Sep 10, 2017 at 19:58
  • \$\begingroup\$ yes en.wikipedia.org/wiki/Media-independent_interface \$\endgroup\$ Commented Sep 10, 2017 at 20:53
  • \$\begingroup\$ who was the idiot that -1 without a comment \$\endgroup\$ Commented Jan 21, 2019 at 3:33

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