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SPLD Reference

https://www.arrow.com/en/categories/programmable-devices/programmable-logic-devices/splds

CPLD Reference

https://www.arrow.com/en/categories/programmable-devices/programmable-logic-devices/cplds

I am trying to learn how to make a cpu, but am still far away from college. So I thought I would ask here since I got alot out of it last time. Could someone help me make a basic cpu from a CPLD, 64K-bit-SRAM, EEPROM, Basic logic gates (AND, OR, NOR, NAND), MUX, DEMUX, and a program counter, or point me in the right direction?

I know about ben-eater and that's what i'm going for but I want to make a cpu that uses programmable logic.

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closed as too broad by Chris Stratton, Leon Heller, DoxyLover, PeterJ, Dave Tweed Sep 11 '17 at 1:57

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

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    \$\begingroup\$ Hi, while your goals are wonderful, this type of question doesn't fit with the mission of stack exchange sites - these are not discussion forums or general posting sites, but restricted only to specific questions which can have lasting answers right here. Generally speaking for this type of thing you should start by reading CPU design references and existing project notes, and preferably do a lot of simulation before you build actual hardware. When I did this years ago I used the MIT Open Coursewear 6.004 notes - they change that site around from time to time so others may be better. \$\endgroup\$ – Chris Stratton Sep 10 '17 at 17:32
  • \$\begingroup\$ Sorry, Do you think you could point me in the right direction? I've been searching for awhile now. I just thought here would be a good place. If you know of a book or resource, that would help immensely. just saw your update. \$\endgroup\$ – Jonathan S. Sep 10 '17 at 17:34
  • \$\begingroup\$ Worry first about understanding how a CPU works before you pick the target hardware for implementation. And again, start with a simulator as it's a lot easier to rip-out and fix wires in a text editor. It may even be worth using an FPGA before going to your relatively discrete solution, where you'll start not only needing to wire the CPLD to everything else but need additional gear to program the EEPROM, etc. \$\endgroup\$ – Chris Stratton Sep 10 '17 at 17:38
  • \$\begingroup\$ I am fresh out of high school, and i don't have the knowledge to use something like logisim. i have it but haven't a clue how to use it. I'm starting with breadboards, is that a good idea? i have an arduino for programming. \$\endgroup\$ – Jonathan S. Sep 10 '17 at 17:42
  • \$\begingroup\$ could we message on google hangouts or something? the delay is terrible. \$\endgroup\$ – Jonathan S. Sep 10 '17 at 17:44
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16 bit addressable memory puts you out of CPLD (and definitely SPLD) range implementations.

You can try this as a good starting point, with an 8bit cpu with 6 bit addressing as a starting point. Read the pdf first to understand the design.

Rather than focus on the device, you need to understand the VHDL implementation of a cpu... the size of which will drive device selection.

You might read this by Colin Riley ....a great walk through a design for a Xilinx FPGA cpu implementation.

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