# Negative recommended intensity on read of logical 1 D-latch octal register

I am very new to electronic design, even if I do have some bases in electric design.

For an hypothetical circuit I'm designing, I need some D-latches to operate as 8 bit registers. Searching for chips suited for this, I found this datasheet : http://www.ti.com/lit/ds/symlink/cd74ac373.pdf

While reading the specifications, something struck me : the "High level output voltage" entry on the recommended operation conditions table suggests by it's test conditions, that the current on the pin be negative when reading a logical 1.

While this may also be misinterpretation of the table causing this nonsense, if it's not, how to design circuits such that they do accept the negative current (maybe shift it to 0 mA ?)

Sorry again if my question is dumb.

• You mean current? Sep 10, 2017 at 20:36
• Oh, yeah. In french we say 'Intensité". Going to edit that. Sep 10, 2017 at 20:40

## 1 Answer

By electronic convention, current flowing from a positive source Voh is negative current, then into a load becomes a positive current.

These specs also indicate the incremental or effective series resistance (ESR)of the driver , which is the RdsOn value of each FET for low and high.

• Sachiko, google "passive current convention" Sep 10, 2017 at 20:45
• Yes Vdd is positive, Vss is negative and usually we define the negative as 0 V with a gnd symbol, even if it is floating. Except when I had a 1963 MGB convertible, the Brits decided positve ground was a better idea. Sep 10, 2017 at 20:46
• A pin at driven high is expected to source current into the load (Thus the pin current is negative and the load current positive), while a pin driven low will be sinking current from the load (which is sourcing the current) hence positive current at the pin and negative current at the load). Sep 10, 2017 at 20:46
• So basically, it's simply a convention, both are outputting currents of the same sign, while at different values (with for exemple, -4 mA at 3 V for high and 12 mA at 3V for low, following the convention) ? Sep 10, 2017 at 20:46
• The - mA sign indicates supplying positive V or a load in the return line, but you will learn from Kirchoff KCL rules the node current adds to 0 Sep 10, 2017 at 20:48