There are so many resources online talking about how to represent and extend signed numbers in Verilog, but I still can not get it. Let's say I have a number 244, which is 'b1111_0100, or 'hF4. If I want to represent this number in signed decimal, should I need to declare the size with one extra bit for the sign?
8'sd244 or 9'sd244 // signed 244? 8'sb1111_0100 or 9'sb1111_0100 // which one is correct 244? 8'shF4 or 9'shf4 // Do I need 0FA, or it is assumed?
Even more confusion comes with negative numbers: do I need to represent them in 2's complement format? How about the size? It would be nice if someone could give an explanation with example in the