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schematic

simulate this circuit – Schematic created using CircuitLab

I have a synchronous FIFO. The depth of the FIFO is 32. Everytime the FIFO has 7 or any "n" unique elements inside it, "unique" signal goes HIGH. How do I test the "unique" signal going high in SystemVerilog or UVM? How would my scoreboard look like?

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  • \$\begingroup\$ An alternative approach might be to use a queue to model the FIFO. Moreover, when every element is pushed into the DUT (and to the reference model/queue), one should check whether there are n distinct elements in queue or not (using unique built-in method). And expect unique signal to be high when the reference model queue has sufficient number of distinct elements. When a read happens, one should pop respective element from the queue. \$\endgroup\$ – sharvil111 Feb 13 '18 at 12:51
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You don't really need a UVM testbench for a simple test like this. Send in randomized inputs, predict when unique should be high, and check if this condition is met.

The key work here is to predict. This would be your scoreboard, checker or anything else you want to call it.

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