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I read the answer here Difference between latch and flip-flop? which says that the only difference is flip flops need clock and the output of latches don't depend on clock.

I am reading Morris Mano book on digital logic which clearly says that " latches are level sensitive devices or level triggered and flip flops are edge triggered devices" which means latches also depend on clock.

Now which one is correct? Can someone please explain it clearly?

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  • \$\begingroup\$ My experience is that latches have an enable signal. When the enable signal is inactive the data input signals are ignored. When the enable signal is active the data inputs flow continuously through the device (sometimes called transparent) and are responded to immediately until the enable goes inactive again. \$\endgroup\$ Sep 11, 2017 at 16:35

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A sequential element is called a flip flop if it is edge triggered. There must hence be an input to the flip flop that on transitioning 'triggers' it to evaluate the output. In other words, a flip-flop is an element that maps the inputs to the outputs at an instant when there is a level transition of this 'triggering' signal. If this triggering must occur periodically, a clock is connected to this input.

Similarly, a sequential element is called a latch if it is level triggered. There may hence be an input to the latch which on being in a certain level 'triggers' it to evaluate the output (Or, you could forego designing it with such a signal and it would still be called a latch). A latch hence is 'enabled' when this triggering input is at a certain level. It would be more appropriate to see this signal as an enable signal than as a clock. This is because a clock is a signal that is used to identify specific instants of time at its edges.

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To understand the difference between a latch and a flip-flop. let us take up the example of D-latch and D-flip-flop. In D-Latch D value copies to Q whenever the clk value is 1. In D-flip-flop D copies to Q only on a rising positive clk edge, i.e. Q will be D only when the clk value changes from 0 to 1; the D-flip-flop maintains the previous state irrespective of D value in all other cases. Difference between latch and flip flop using timing diagram

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  • \$\begingroup\$ M SAI NITHIN - Hi, Please note that when a post copies or adapts material (e.g. text, image, photo etc.) from elsewhere, that content must be correctly referenced. For online content, the source webpage / PDF / video etc. should be named & linked as a minimum (see the rule about references for offline books / articles). Therefore please edit your answer to add the appropriate source reference (source name & link) for that diagram & remember to include references in future. Thanks. || As you're new here, please see the main site rules in the tour & help center. \$\endgroup\$
    – SamGibson
    Dec 6, 2023 at 3:21

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