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I am trying to synthesize around 3000 different modules. The verilog codes for these were generated using a python code.

Is it possible to automate the synthesis and compile the results such as number of LUTs used and critical path?

NOTE: I am currently using Xilinx ISE.

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The ISE GUI generates a "command.log" file in the project directory. That contains the command lines for synthesis, PAR etc.

Copy/paste these command lines into a terminal (cd to the right place first!) and see what they do. Edit them and make simple changes to see how they work, and look at the documentation - yes these command lines are documented if you look in the right place (I'm away from ISE just now and I can't remember it offhand).

Then hack them around in Python, to script the process for every file in your project, and extract info from the Synthesis Report (.syr) file etc, however you want.

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