As I understand it, and please correct me if I'm wrong, one of the main drawbacks of using an S/R flip flop is that it can find itself in an illegal state with both S & R both with a logic value of 1. The J/K flip flop remedies this by having a clock circuitry prevent the forbidden state.

With this in mind, are there any uses for S/R flip flops in digital design, or have they all been abandoned in favor of J/K and D flip flops?

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    \$\begingroup\$ SR FFs are the base elements for the other FFs. \$\endgroup\$
    – Eugene Sh.
    Sep 12, 2017 at 15:17
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    \$\begingroup\$ Any FF or latch will be in illegal-state, if you activate both Clear/Preset or Set/Reset, etc. \$\endgroup\$ Sep 12, 2017 at 16:45

1 Answer 1


SR flip-flops are still useful in constructing asynchronous sequential logic circuits. Normal clocked flip-flops internally are just of that kind. Complex sequential circuits are at least on paper possible to construct using SR flip-flops, but designers generally use clocked flip-flops to keep the gate and transmission delays out of the major role. Complex sequential logic simply is much more easy to design and test if all state changes happen as clocked.


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