Here is my problem:

enter image description here

pretend each of the multiplexers are hooked up to the corresponding bit of each Byte. The first multiplexer is hooked up to the first bit of each of the Bytes (0 - 3). The second multiplexer is hooked up to the second bit of each Byte (0 - 3) and so on. My problem is, is that i don't have 16 input multiplexers. How can i take 4 input multiplexers and get an equivalent 16 input multiplexer?

edit (by Steven)
Given the comments and the three downvotes it seems that the diagram isn't clear for everybody. At the right you have an array of 16 bytes (ignore "program instructions"). John wants a way to multiplex all of the 16 LSBs to one output, all of the next LSBs to a second output, and so on, for all 8 bits. That's the 8 blocks on the left, 8 muxes. They only show 4 inputs and 2 select lines, because John's problem is that he can't find a 16-input mux. HTH.

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    \$\begingroup\$ This makes absolutely no sense. I suspect that the underlying problem is you don't understant what a processor does. I can't even imagine how you think a command line processor has anything to do with a hardware multiplexer. You are envisioning some architecture, but without understanding how computers work, and expecting us to see what's in your head. \$\endgroup\$ – Olin Lathrop May 29 '12 at 23:02
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    \$\begingroup\$ @OlinLathrop, I have reopened this after an edit has been performed.I believe it is more clear now but others can disagree and let me know. \$\endgroup\$ – Kortuk May 30 '12 at 4:44
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    \$\begingroup\$ Still nonsense, as far as I can tell. \$\endgroup\$ – The Photon May 30 '12 at 5:02
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    \$\begingroup\$ @ThePhoton - I seem to understand it, and I know I'm a bit slow at times :-) \$\endgroup\$ – stevenvh May 30 '12 at 5:33
  • \$\begingroup\$ @stevenvh, you seem to have figured out what he wanted, but as presented the question is still nonsense. Why are some of the lines on the left labelled "in" and some "out"? How does a 16:1 mux feed a 16 byte memory? What do "program instructions" have to do with it? \$\endgroup\$ – The Photon May 30 '12 at 16:09

You simply have to add another level of multiplexers.

enter image description here

What you have now is the left part of this circuit: 4 times four inputs, giving 4 outputs. Use a fifth multiplexer to select one of those outputs. Since you have 16 inputs you need 4 select lines (2\$^4\$ = 16). That's the A, C, D and E lines. Note that the four muxes at the left use the same select lines.

If you want to select the input the arrow points to you'll have to set D = 1, E = 1, and for the right mux A = 0 and C = 1.

The 74HC153 is a dual 4-to-1 multiplexer.

Supercat's tri-state buffers are an excellent idea (don't forget to upvote), and it came to me naturally when I was writing the edit to OP. The multiplexer solution needs a few more parts, but can be implemented in a CPLD, I'm not sure if they support tri-state logic internally. (They do for I/O.)

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    \$\begingroup\$ @John - Glad to be of help :-) \$\endgroup\$ – stevenvh May 30 '12 at 5:30

While the approach suggested by stevenvh will work given the particulars of your question, it would in many real-life scenarios not be the most practical solution. If there are 16 8-bit registers, selecting among them would require 40 4-input multiplexers (five for each bit). Every four 8-bit registers that are added will require at least eight more four-input multiplexers. If you can use devices with three-state outputs (high/low/floating), it may be more practical to wire each register word to an 8-bit bus. At any given time, one register will be enabled to drive its data onto the bus; all of the other registers will leave the bus alone so the selected word can drive it. Rather than using forty 4-bit multiplexers to read an 8-bit value, one would instead use one 8-bit three-state bus driver for each register (16 of them), along with two 74HC138 (or similar) chips, one of which would control the first eight registers' output enables, and one of which would control the last eight registers' output enables.

While there are some situations where three-state logic isn't usable, there are others where it can greatly reduce the amount of circuitry required to do certain things.

  • \$\begingroup\$ I commented on this good idea in my answer. Do you know if this can be implemented in a CPLD? Do CPLDs support tri-state internally? \$\endgroup\$ – stevenvh May 31 '12 at 8:25
  • \$\begingroup\$ @stevenvh: CPLDs and FPGA's generally support 3-state outputs, but do not support 3-state logic internally. On the other hand, CPLDs are often pretty good at synthesizing moderate-sized multiplexers internally. If the design is such that the registers could sensibly be split between two or four chips (especially given that, at some parts of the CPLD price spectrum, two small CPLDs may be cheaper than one twice-as-big one), it may be useful to use a hybrid approach. If each CPLD is responsible for four or eight byte-wide registers, for example, it may make sense to wire 8 pins of each CPLD... \$\endgroup\$ – supercat May 31 '12 at 15:57
  • \$\begingroup\$ ...to corresponding pins on the others. Then have one CPLD output a byte while the others (if they need to do anything with the value) read it. \$\endgroup\$ – supercat May 31 '12 at 15:58

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