# How can this negative voltage spikes be explained?

I'm tried to understand capacity measurement circuity. A basic method is to load a capacitor with a constant current and show how long it took to reach 50% voltage for example. Capacity = (Current * delta T) / Voltage

Basic Circuity:

simulate this circuit – Schematic created using CircuitLab

The image shows the start/end of the charging, and decharging through Q1. After 245µs (after the capacitor voltage is 0V for several µs) charging starts again. What I can not explain is the sudden negative voltage spike when the decharging transistor is turned off (245µs).

Can some one explain that? Could this only be a simulation problem (LTSpice)?

I replaced the transistor with a "voltage controlled switch" (SW) and there was no spike at all.

The current source is a 2 transistor current source (1.5µA).

• We don't know how your simulation looks like, likely you have somewhere some inductanec. Commented Sep 13, 2017 at 15:13
• You should put the whole schematics. In this way it would be much easier to help you. Commented Sep 13, 2017 at 20:07

The negative spike is not due to inductance: when it happens, C1 is simply charged to a negative voltage, after which the current source charges it with positive current, and the voltage increases.

I'll bet on the current source transistor being a PMOS (or a PNP) which has drain-gate (or collector-base) capacitance.

Switching this transistor ON is done by bringing the gate/base down a few volts.

This leaks some charge through the drain-gate capacitance.

Since C1 has a very low value, a few pF drain-gate capacitance on the PMOS or PNP will be enough to change its voltage.

This circuit does not measure C1: it measure the sum of the capacitances of C1, the current source, the comparator input capacitance, Q1's collector capacitance, etc. Can't be helped!...

For the same reason, turning Q1 on leaks some charge through its Cbc, which explains the positive spike at the end of charge.

• I suspect you are correct, and the simulator is providing an infinitely fast rise and fall time on the transistor base. This is easily checked. Replace R2 with 2 500 ohms in series, and a 1000 pF cap from the middle junction to ground. Commented Sep 13, 2017 at 18:13
• @peufeu Yes indeed it's a PNP-Transistor based current source. I didn't know that the influence is that large. So this kind of measurement for low capacitance isn't suitable I guess? Commented Sep 13, 2017 at 20:41
• @peufeu What I still don't understand then is, why there are no spikes (in either way) if I replace the transistor with a kind of ideal mechanical switch which was modeled as simple voltage controlled switch in LTSpice. My conclusion was that it must has something to do with Q1. Commented Sep 13, 2017 at 20:48
• The ideal switch is ideal, it has no capacitance ;) the transistor has a few pF... Commented Sep 13, 2017 at 21:01