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D flip-flops with set and reset can only work when set = 1 = reset, and the Q value depends on D and clock, but in the SAR logic circuit shown below, we find set and reset aren't equal to 1 at the same time:
So, I am curious about how the D flip-flop works in SAR logic to let the SAR logic output become like:
D9=1, D8=0, ... D0=0
D9=0, D8=1, D7=0, ... D0=0
D9=0, D8=0, D7=1, D6=0, ... D0=0
and become D9=0, D8=0, D7=0, D6=0, ... D1=0, D0=1 in the end.
The top group of Dffs generate a wavefront thusly
000000 <- upon the initial reset 100000 <- upon first clk rising edge 110000 <- upon second clk rising edge 111000 <- upon third 111100 111110 111111
and the bottom group implement the testing/latching behavior of binary search. The comparator logic-level determines whether the bit just set high, as the wave moves along to the right, will remain high after the wave moves one bit to the right.
The feedback from bit 7 "Q" to bit 8 "CLK" [ the triangle input ] is the digital signal performing the sample-the-comparator-output, and make that binary-search activity for that bit (which is controlling a DAC).
Have you drawn a timing diagram? Start with "reset", and "clock". and some random "Comp" NRZ pattern. And the Q outputs of all the FFs.
The content of the upper "register" is a "moving 1", because the input of the register is a "0" ...
The first FF is set, the others are reset.
So the register shift shows successively: 10000, 01000, 00100, 00010, 00001 ...
Here is a simulation of the behavior of a 4 bits ADC, SAR type.
Note also that there is a "little" error when testing the original picture ...
The "rst" pulse is also the "start" convert.
