D flip-flops with set and reset can only work when set = 1 = reset, and the Q value depends on D and clock, but in the SAR logic circuit shown below, we find set and reset aren't equal to 1 at the same time:
So, I am curious about how the D flip-flop works in SAR logic to let the SAR logic output become like:
D9=1, D8=0, ... D0=0
D9=0, D8=1, D7=0, ... D0=0
D9=0, D8=0, D7=1, D6=0, ... D0=0
and become D9=0, D8=0, D7=0, D6=0, ... D1=0, D0=1 in the end.