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This is the code:

always @(*)
  case(NormalCtrl[7:6])
    2'd0: TrigA = 0;
    2'd1: TrigA = TrigAA;  
    2'd2: TrigA = TrigBA;
    default: TrigA = TrigA;
  endcase

This is the resulting RTL schematic (Vivado 2015.1): Schematic of the above code.

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    \$\begingroup\$ apparently because you've asked for a combinational latch. Why aren't you designing synchronous logic with a clock? \$\endgroup\$
    – user16324
    Commented Sep 15, 2017 at 10:15
  • \$\begingroup\$ I haven't asked anything, it's not my code. \$\endgroup\$
    – user61801
    Commented Sep 15, 2017 at 11:45
  • \$\begingroup\$ Ah. If you haven't asked anything, there is no need for an answer. And the RTL shows one mux for the data source, one for the enable. So all is good. \$\endgroup\$
    – user16324
    Commented Sep 15, 2017 at 11:49
  • \$\begingroup\$ @user8352 you are right, my bad. \$\endgroup\$
    – user61801
    Commented Sep 15, 2017 at 12:19
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    \$\begingroup\$ When the input equals 3, the logic says that TrigA should keep its previous value. To keep a previous value you need a storage element, like a latch. This is an example of poorly written Verilog code, if it's not your code you should understand its purpose from whoever gave it to you. \$\endgroup\$ Commented Sep 15, 2017 at 13:49

1 Answer 1

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A level-sensitive latch is inferred when combinational RTL doesn't assign a deterministic value to all possible combination, or the same combinational logic is assigned back to it self (i.e. default: TrigA = TrigA;). Note: for the rest of this answer when I say latch, I'm referring to a level-sentience latch. If I say flop, I'm referring to a edge-sensitive flip-flop.

The mux TrigA_i is being used as to select the D input of the latch.

The mux TrigA_i_0 is begin used as to determine if the latch should be transparent (NormalCtrl[7:6]!=2'b11) or closed (NormalCtrl[7:6]==2'b11). Functionally this mux is equivalent to a 2-input NAND gate.

There are two possible reasons the synthesizer decider to use a mux as the latch gate instead of a nand gate:

  1. Balanced timing of the two paths of to the latch. A single nand gate has less propagation delay than a mux. If a nand gate were used, then a latch's enable could open or close before the data is ready which is a possible risk for a glitch. Buffers could be added for balancing propagation paths. However this may use more area and the timing difference has higher margin of error than using the same (or very similar) mux gates.
  2. Less likely but still possible, the synthesizer doesn't have a great logic optimizer or there are constraints put on the synthesizer that limits optimization.

Why not use one mux whose output feeds back into itself you may ask. Muxes are not intended to be used value storage. Synthesis would have a hard time to guarantee setup/hold times to prevent meta-stability. Plus, there is also a risk of a data glitch as the select bits change form 2'b00 to 2'b11 (intermediate 2'b01 or 2'b10). Synthesizers use real latches to reduce these risks (know setup/hold requirements, non-complex inputs).

In general latches should be avoided in most RTL designs. Latches are asynchronous and therefore timing is critical to be done correctly. There are a handful of conditions where using latches is necessary. In these scenarios it is best to keep the latch as simple as possible and the gate-enable pin should be driven by a direct flop (no intermediate logic) to avoid glitches.

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