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I was wondering about this the other day when I was explaining binary and hexadecimal to a friend of mine and this came up. The question goes something like this:

How exactly do instruction execution speeds relate to clock speeds in modern computers?

For instance, say a clock signal of 1 MHz is used by a computer processor. The processor will execute operations on the edge of that clock (on the negative edge if I'm not mistaken), but this doesn't mean that a full instruction will be executed for each clock cycle.

To have a more specific example, if an Intel x86 processor has a MOV BX, 45 command, I am assuming that it will take several clock cycles to complete this since the number 45 has to be generated, and the BX register has to be located and so on. Maybe this one might be a single clock cycle since it is an immediate value being moved into a register, but hopefully this kind of explains my question. Maybe a JNE command would be a better example.

On top of this, there is the fetch-decode-execute cycle which would reduce the instructions-per-clock ratio to less than 1:1, is that correct? Please forgive me if I totally misunderstand how this stuff works. I am very interested in it and know that lots of you know quite a bit about it. Please feel free to shed some light on my ignorance :D

Thank you so much

Chris

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  • \$\begingroup\$ 1800 MHz Quad core CPU runs a tad faster on my laptop. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Sep 15 '17 at 22:08
  • \$\begingroup\$ Get into microcontrollers and you'll soon understand the relationship. \$\endgroup\$ – Mike Sep 15 '17 at 22:38
  • \$\begingroup\$ Your unfortunate X86 example has a complex clock cycle (as outlined by @pjc50's answer). Some simple microcontrollers have much less clock-cycle complexity - many almost achieve your 1:1 instruction-per-clock ratio. There's a missing link: a master oscillator (sometimes derived from a crystal) generates the cycle timing. It is often an integer multiple or sub-multiple of crystal frequency and varies from chip-to-chip. You have to carefully read a data sheet. \$\endgroup\$ – glen_geek Sep 16 '17 at 0:27
  • \$\begingroup\$ think of clock speed as how fast you press digits on a calculator, realizing at sometimes you have to wait on a result between presses, like 63! for example... \$\endgroup\$ – dandavis Sep 16 '17 at 21:03
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I am assuming that it will take several clock cycles to complete this

It's rather complicated, but see: https://stackoverflow.com/questions/692718/how-many-cpu-cycles-are-needed-for-each-assembly-instruction

There are basically three factors to consider for a simple explanation:

  • Cycles per instruction. This will be specified in the manual for the processor per instruction. Can be as low as 1.
  • Instructions per cycle. Thanks to "superscalar" design and pipelines, you can have multiple instructions in processing at the same time, and potentially "issue" more than one.
  • Operations per instruction. Thanks to SIMD instruction sets, one instruction can operate on quite a lot of values in a single cycle.

Pipelines complicate timings for "branch" instructions like JNE. You might find that it takes one cycle to not branch and a hundred cycles to take the branch - unless the branch predictor has guessed correctly, in which case those costs are the other way round.

Cache misses take rather a long time as well.

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