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This picture is the simulation of D-flip flop with both active low reset and set,and i know active low means when the signal is 0 ,it means on .but how do i know it is active low from this picture?

Q and Q_bar is always 1.8 when set and reset is 0?so for this active low reset and set,if you feed reset and set low signal,the D-flip flop can't operate normally;but for active high reset and set,it can operate normally.Is my thinking correct?

enter image description here

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  • \$\begingroup\$ What do you think "normal operation" should be when both SET and RESET are asserted? \$\endgroup\$ – The Photon Sep 16 '17 at 4:07
  • \$\begingroup\$ like clk is positve edge when D=1,then Q=1,Q'=0; clk is positve edge when D=0,then Q=0,Q'=1 \$\endgroup\$ – Shine Sun Sep 16 '17 at 6:51
  • \$\begingroup\$ That is not normal operation when either SET or RESET is asserted. Why do you expect it to happen when both SET and RESET are asserted? \$\endgroup\$ – The Photon Sep 16 '17 at 15:12
  • \$\begingroup\$ because the D-flip flop in SAR logic,SET or RESET will be asserted \$\endgroup\$ – Shine Sun Sep 16 '17 at 15:54
  • \$\begingroup\$ BTW,is asserted means signal is 1 ? \$\endgroup\$ – Shine Sun Sep 16 '17 at 15:55
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but how do i know it is active low from this picture?

You know the SET and RESET signals are active low, because when they were both high, the input was transferred to the output with each rising clock edge. This means SET and RESET must have been de-asserted when high. Meaning they must be active low signals.

so for this active low reset and set,if you feed reset and set low signal,the D-flip flop can't operate normally;but for active high reset and set,it can operate normally.Is my thinking correct?

An active-high RESET and SET could be implemented by just putting an inverter in front of each of the existing RESETn and SETn inputs. If you did this nothing about the behavior of the circuit would change except the RESET and SET behaviors would happen when the corresponding inputs are high rather than low (and there would be a slight delay in the flip-flop recognizing these inputs). In case both SET and RESET were asserted (which would now mean they were high), you would still see both outputs go high.

Edit

In a comment on another answer you said,

When Set and Reset are both active,you mean both active high? or active low?

I think you misunderstand what "active high" and "active low" mean.

These terms indicate how the circuit is designed, not the state that they are in at an instant in time.

"Active low" means the circuit is designed so that a low voltage (for example, 0 V) indicates a logical "true" value, or a logical "1" or an asserted state; while a high voltage indicates "false", "0" or the de-asserted state.

"Active high" means the opposite. The circuit is designed so that a low voltage indicates "false", "0", or de-assertion, while a high voltage indicates "true", "1" or the asserted state.

To put it in a table, an active-low design might have

voltage    1/0     meaning
--------------------------
0 V         1      asserted
5 V         0      de-asserted

while the complementary active-high design would have

voltage    1/0     meaning
--------------------------
0 V         0      de-asserted
5 V         1      asserted

Given a circuit, you can't change it from active high to active low just by changing its input voltages. You have to change the circuit design to change it from an active low circuit to an active high circuit.

(Caveat: Due to De Morgan's rules, the same physical gate might be used in either an active-low or active-high circuit. But a circuit that implements a NAND gate in active high logic would implement NOR in active low logic)

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When Set and Reset are both active, both outputs are high. If both are released at the same time, the output state is unknown as the function depends on only one being active.

Otherwise, your simulation shows negative clock edge transfers D to Q, Q_bar

Clock works on negative (BF) positive edge in your simulation which is common for CMOS. never both edges as you may have indicated in comments.

FYI, your simulation is "inverted logic" to "std" CMOS D FF logic in all cases, active low RS and negative edge clock.

Beware that many different ways of ASCII representation for active low include /R, R!, R_ and _R and Q,Q _ means Q,Qbar when it is hard to use \$Q,\bar Q\$ using tex \bar - Q_bar might be considered redundant.

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  • \$\begingroup\$ When Set and Reset are both active,you mean both active high? or active low? \$\endgroup\$ – Shine Sun Sep 16 '17 at 6:46
  • \$\begingroup\$ I mean active. You cant have it active both levels. and yours is inverted to most. \$\endgroup\$ – Sunnyskyguy EE75 Sep 16 '17 at 10:49
  • \$\begingroup\$ I disagree about the sense of the clock. Look at the second low pulse of the clock. If the flip-flop were negative edge sensitive, I'd expect a high output after this pulse, but the output in the diagram is low. \$\endgroup\$ – The Photon Sep 16 '17 at 15:31
  • \$\begingroup\$ It's confusing that the signals are named /clk and /D, which might sometimes indicate active low logic. But then there's also /Q and /Q_bar indicating that the slash is not meant to indicate inverted logic but is just part of every signal name (in a Verilog simulator it might just mean these are signals in the top-level module). \$\endgroup\$ – The Photon Sep 16 '17 at 15:32

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