This is the top group of SAR logic,and as you see,it is composed of lots of D-flip flop with set and CLR(reset),and these D-flip flop are active low.
when both set and CLR(reset) are 1 , Q can only depend on D and clk: when set=1,CLR(reset)=0 , Q=0 , Q'=1;when set=0,CLR(reset)=1,Q=1,Q'=0,the truth table is the same as the website,i suggest to see Figure 1: Timing Diagram of a Positive-Edge-Triggered D Flip-flop from this website. http://macao.communications.museum/eng/Exhibition/secondfloor/moreinfo/FlipFlop.html
initial reset : 00000;
first clk rising edge : 10000
second clk rising edge : 11000,... and fifth clk rising edge:11111?
Here is my thinking,if it is wrong,please tell me
The input are Reset and CLK,but if i want 11000 in second clk rising edge ,i must send Reset=0 to let first ouput is 1,but if i do that,the second d flip flop's output must be 0,because the second d flip flop has CLR=0.