# Design reset about top group of SAR logic

This is the top group of SAR logic,and as you see,it is composed of lots of D-flip flop with set and CLR(reset),and these D-flip flop are active low.

when both set and CLR(reset) are 1 , Q can only depend on D and clk: when set=1,CLR(reset)=0 , Q=0 , Q'=1;when set=0,CLR(reset)=1,Q=1,Q'=0,the truth table is the same as the website,i suggest to see Figure 1: Timing Diagram of a Positive-Edge-Triggered D Flip-flop from this website. http://macao.communications.museum/eng/Exhibition/secondfloor/moreinfo/FlipFlop.html Is it possible to let a~e become like

initial reset : 00000;

first clk rising edge : 10000

second clk rising edge : 11000,... and fifth clk rising edge:11111?

Here is my thinking,if it is wrong,please tell me

The input are Reset and CLK,but if i want 11000 in second clk rising edge ,i must send Reset=0 to let first ouput is 1,but if i do that,the second d flip flop's output must be 0,because the second d flip flop has CLR=0.

• Normally we indicate active low logic with a "ball" on the input pin or a bar over the pins name. If you want to use active low logic, your schematic would be more clear if you follow this convention. In particular, sometimes some inputs to a flip-flop are active low while others are active high, so you should indicate individually for each input what the logic sense is. – The Photon Sep 16 '17 at 15:27
• Also, the possibility of your logic to take a particular state has nothing to do with whether it's active low or active high. – The Photon Sep 16 '17 at 15:29
• So you means D-flip flops ,in SAR logic ,are not totally the same? – Shine Sun Sep 16 '17 at 16:00
• When you say "SAR logic" do you mean the logic that controls a Successive Approximation Register ADC? I don't think there's any reason the flip-flops used in this logic should be any different from any other flip-flops. – The Photon Sep 16 '17 at 16:02
• I thought "sometimes some inputs to a flip-flop are active low while others are active high" this sentance means some flip flop may be different from the others. – Shine Sun Sep 16 '17 at 16:16