# Basic doubt on clear and preset inputs

I am having a basic doubt regarding the working of preset and clear inputs.

Consider these two figures:-

Here in figure 1, if clear is 0, then Q will be 0 from 1.

But if its active low signal as shown in figure 2 then if clear is 0, then it will be inverted and clear input will be 1. So how will the output Q be 0 if clear input =1 ? I think it should not be inverted so that we can directly pass the clear input which is 0 and get output Q as 0.

I am not able to understand the meaning of active low signal and it's use here. What is the actual meaning of active low signal ? Is it just like attaching a NOT gate for input or does it mean that circuit will be active for low inputs but the inputs remain the same and not get inverted?

• The meaning of "active low" and "active high" is discussed in my answer to another question just earlier today. Commented Sep 16, 2017 at 21:24
• If I assert CLR it means "I want to clear the output". In this design, in order to do that we must apply a low voltage to the CLR input. So we say that CLR is an active low input (it is asserted when a low voltage is applied). Commented Sep 16, 2017 at 21:26
• Also, remember that when engineers talk about their circuit, they're limited to what human language can express. So they might not always be 100% careful about distinguishing what "set to 1" or "asserted" or whatever means, and you have to figure it out from context. If in doubt, read the schematic. (This is why we always like schematics in questions about circuits). Commented Sep 16, 2017 at 21:35
• @The Photon, Please answer my one doubt. In figure 1, if we give CLR=0, then we get Q=0. But in figure 2, If we give CLR=0, then it will be inverted and CLR=1. So how will CLR=1, give Q=0 ? I just want to know this. Commented Sep 16, 2017 at 22:16
• I interpret figure 2 differently from you. I think by including the bubble on the CLR input, they're just being more clear that this is an active low signal, and the behavior is the same as the circuit in figure 1. Really, you need to have the truth/transition table for the gate to know what it's behavior is. The symbol might be sloppily drawn. Commented Sep 16, 2017 at 22:23