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I am having a basic doubt regarding the working of preset and clear inputs.

Consider these two figures:-

enter image description here

enter image description here

Here in figure 1, if clear is 0, then Q will be 0 from 1.

But if its active low signal as shown in figure 2 then if clear is 0, then it will be inverted and clear input will be 1. So how will the output Q be 0 if clear input =1 ? I think it should not be inverted so that we can directly pass the clear input which is 0 and get output Q as 0.

I am not able to understand the meaning of active low signal and it's use here. What is the actual meaning of active low signal ? Is it just like attaching a NOT gate for input or does it mean that circuit will be active for low inputs but the inputs remain the same and not get inverted?

Please help.

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  • \$\begingroup\$ The meaning of "active low" and "active high" is discussed in my answer to another question just earlier today. \$\endgroup\$ – The Photon Sep 16 '17 at 21:24
  • \$\begingroup\$ If I assert CLR it means "I want to clear the output". In this design, in order to do that we must apply a low voltage to the CLR input. So we say that CLR is an active low input (it is asserted when a low voltage is applied). \$\endgroup\$ – The Photon Sep 16 '17 at 21:26
  • \$\begingroup\$ Also, remember that when engineers talk about their circuit, they're limited to what human language can express. So they might not always be 100% careful about distinguishing what "set to 1" or "asserted" or whatever means, and you have to figure it out from context. If in doubt, read the schematic. (This is why we always like schematics in questions about circuits). \$\endgroup\$ – The Photon Sep 16 '17 at 21:35
  • \$\begingroup\$ @The Photon, Please answer my one doubt. In figure 1, if we give CLR=0, then we get Q=0. But in figure 2, If we give CLR=0, then it will be inverted and CLR=1. So how will CLR=1, give Q=0 ? I just want to know this. \$\endgroup\$ – Zephyr Sep 16 '17 at 22:16
  • \$\begingroup\$ I interpret figure 2 differently from you. I think by including the bubble on the CLR input, they're just being more clear that this is an active low signal, and the behavior is the same as the circuit in figure 1. Really, you need to have the truth/transition table for the gate to know what it's behavior is. The symbol might be sloppily drawn. \$\endgroup\$ – The Photon Sep 16 '17 at 22:23
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The signals are active low, because are inverted - the line above them is a inverting symbol. If CLEAR is 1, nothing happens, until it becomes 0, then the output is cleared. If PRESET is 1, nothing happens, until it becomes 0, then the output is set.

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  • \$\begingroup\$ I am sorry, I added the wrong picture before. Now I have edited the picture of SR flip flop. I watched this video youtube.com/watch?v=mXoQ4WAQ0qk about preset and clear. In the edited figure of SR flip flop, how will CLR=0 to the flip flop give output Q as 0 ? Because after giving CLR=0, the input to the circuit will be value 1 which is equivalent to CLR=1. \$\endgroup\$ – Zephyr Sep 16 '17 at 20:17
  • \$\begingroup\$ @Zephyr Read my answer again if CLR=0, then Q=0. look the truth table from the video. \$\endgroup\$ – Marko Buršič Sep 16 '17 at 20:23
  • \$\begingroup\$ I figure 1, if we give CLR=0, then we get Q=0. But in figure 2, If we give CLR=0, then it will be inverted and CLR=1. So how will CLR=1, give Q=0 ? \$\endgroup\$ – Zephyr Sep 16 '17 at 20:29

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