4
\$\begingroup\$

circuit schematic

What does this circuit do? It looks a little bit like a flip-flop to me, but it doesn't exactly match the circuit for an SR flip-flop on Wikipedia.

Is this just a different way to implement an SR flip-flop, or is it something else entirely?

Thanks!

Edit: To clarify, DTR and RTS in this circuit are both 3.3V level signals, not RS-232 level signals. This circuit comes from this schematic. (So, DTR and RTS are coming from the CP2104 USB-to-serial converter chip.)

\$\endgroup\$
1
  • \$\begingroup\$ it has no power supply, so it's certainly not a flip flop. Let RTS be low, and DTR be high, what are the outputs? Now examine the other 3 combinations of low and high for the inputs and examine what the outputs do. \$\endgroup\$
    – Neil_UK
    Commented Sep 17, 2017 at 5:19

1 Answer 1

3
\$\begingroup\$

It's a cute way of drawing the schematic. A less-cute drawing would look like:

schematic

simulate this circuit – Schematic created using CircuitLab

Now, it is pretty easy to see that the RTS line needs to pull down (be LO) in order to have an impact on RESET and that the DTR line needs to pull down (be LO) in order to have an impact on GPIO0. Both the RESET and GPIO0 lines are also now very clearly also simply "open-collector outputs," so they will need some kind of passive pull-up (at least) in order to have a definite output voltage in all cases.

With only a very slight moment's consideration, it's also clear that if both DTR and RTS are pulled LO then neither GPIO0 or RESET are actively pulled down. The same is also true if both DTR and RTS are pulled HI. So the only way either of GPIO0 or RESET can be actively held LO is if RTS and DTR are different from each other, with the one held LO actively controlling its associated output by pulling it LO, too.

So if DTR=HI and RTS=LO then RESET is actively pulled low and if RTS=HI and DTR=LO then GPIO0 is actively pulled low. Otherwise, neither GPIO0 or RESET is actively pulled LO.


The above assumes that DTR and RTS are logic-level signalling. However, those lines may be RS-232 signals since those pin names are also often found with RS-232 devices. You don't say. But if they are, then everything I mentioned above is put into jeopardy. With RS-232, a MARK is from -3 to -15 volts and a SPACE is from +3 to +15 volts. And it's rather likely that the whole scheme winds up damaging the two BJTs as well as whatever is connected to GPIO0 and RESET.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.