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I read that output frequency of asynchronous counter will be \$\frac{f_{in}}{2^n}\$ where \$n\$ is number of flip flops and \$f_{in}\$ is input frequency.

In synchronous counter will the output frequency always be \$\frac{f_{in}}{2}\$ ? As clocks are activated simultaneously for all flip flops, each flip flop will get activated simultaneously but only during a positive or negative edge so all flip flops will have output frequency \$\frac{f_{in}}{2}\$.

Am I correct ? I didn't find information about output frequency of synchronous counter anywhere.

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  • \$\begingroup\$ Keep searching. \$\endgroup\$ – Andy aka Sep 17 '17 at 8:55
  • \$\begingroup\$ The short answer is no. \$\endgroup\$ – Brian Drummond Sep 17 '17 at 10:49
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If you have a binary counter, modulo M = 2^N, where N is the number of flip-flops, then the frequency of the most significant bit (I assume this is what you're referring to with "output frequency") will be f/M = f/(2^N), where f is the input frequency. This regardless if the counter is synchronous or asynchronous. (Yes, in a synchronous counter, the clock is fed to all the flip-flops, but there is some combinational logic which, taken the outputs of the current state, will determine the inputs of the next state, to actually have the counter to ... count). The duty cycle will be 50%.

If your counter is modulo M, with M < 2^N (think of a decade counter such as 74LS90), then the frequency of the MSB will be f/M, but:

  • The frequency of the MSB is no more f/(2^N), despite there are N flip flops.
  • The duty cycle may not be 50%.
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  • \$\begingroup\$ Thanks for your answer. But I am still not able to understand how will frequency in synchronous counter will be fin/2^n . In asynchronous counter we are getting that 2^n factor because each flip flop's clock depends on the clock of previous flip flop and hence time period gets multiplied by 2 for every flip flop. But in synchronous counter no such thing happens because all flip flops operate independently on clock simultaneously which are negative or positive edge triggered. I am talking about normal modulo m binary counter. \$\endgroup\$ – Zephyr Sep 17 '17 at 11:34
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    \$\begingroup\$ In synch. counters, all the FF share the same clock. But, except the first FF, all the other FF'outputs won't always toggle at each rising edge. Look at this figure (a 4-bit counter): sub.allaboutcircuits.com/images/04353.png . In particular the first output will toggle with a frequency of f/2. The second with f/4, etc. In fact, it must count 0000, 0001, 0010, 0011, etc. \$\endgroup\$ – next-hack Sep 17 '17 at 12:50

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