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I drow the ring counter schematic,but the last two flip flop simulation signal didn't "shift".

My D-flip flop is designed as set=1,then Q=0; reset=1,then Q=1;

set=1=reset,then Q=1,when D=1 occur at positive edge clk.

set=0=reset,then Q=1=Q_bar

Here is my thinking,if it is wrong ,or you have other ways to let my simulation become correct, please tell me.

At first,the output should be 1 0 0,but mine is 1 1 1;i think it is because my flip flop's output,Q and Q_bar,are 1 when set=reset=0.To modify the circuit of my d-flip flop,is there a way that only change (set=reset=0,then Q=Q_bar=1) to (set=reset=0,then Q=Q_bar=0)??

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  • \$\begingroup\$ Just to remove any doubt about the state of your unused SET and RESET inputs you should pull them up to +V or force them to the unasserted level. \$\endgroup\$ – Entrepreneur Sep 17 '17 at 14:03
  • \$\begingroup\$ The flip flop schematics is very confusing: you're missing all the dot connections when 3 or more signals are connected.... \$\endgroup\$ – next-hack Sep 17 '17 at 14:06
  • \$\begingroup\$ Entrepreneur and next-hack : sorry,i don't understand your meaning,can you explain your meaning in more detail ? \$\endgroup\$ – Shine Sun Sep 17 '17 at 14:08
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    \$\begingroup\$ Connect your unused RESET, SET, SET inputs to VDC. \$\endgroup\$ – Entrepreneur Sep 17 '17 at 14:30
  • \$\begingroup\$ thankyou,it works \$\endgroup\$ – Shine Sun Sep 17 '17 at 15:11
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Just to remove any doubt about the state of your unused SET and RESET inputs you should pull them up to a logic "1". Connect your unused RESET, SET, SET inputs to VDC.

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